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CAM35C44 датащи(PDF) 8 Page - SMSC Corporation

номер детали CAM35C44
подробное описание детали  Infrared Communications Controller Chip CameraFR
PDF  50 Pages
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производитель  SMSC [SMSC Corporation]
домашняя страница  http://www.smsc.com
Logo SMSC - SMSC Corporation

CAM35C44 датащи(HTML) 8 Page - SMSC Corporation

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8
NAME
TOTAL
PINS
SYMBOL
BUFFER
TYPE
DESCRIPTION
DMA Request
1
DRQ
O12
The DRQ pin is forced active by
the CAM35C44 when byte
transfers to the host using DMA
are required. DRQ goes inactive
when the transfer has been
completed. The active DRQ pin-
state is determined by the
DRQ_LEV bit in CR01 (see page
22).
DMA Acknowledge
1
DACK
I
The DACK pin is forced active by
the host DMA controller to
acknowledge CAM35C44 transfer
requests. DACK goes inactive
following the transfer command.
The active DACK pin-state is
determined by the DAC_LEV bit in
CR01 (see page 23).
Terminal Count
1
TC
I
TC indicates that a DMA transfer
is complete. TC is only acknow-
ledged when DACK is active.
ISA I/O Read/
Non-ISA Read/Write
Control
1
nIOR/RnW
I
The active low nIOR input is
issued by the host to execute I/O
read commands when an ISA
read/write-styled host interface
type is selected (TABLE 3). The
RnW input is used to determine
the I/O command type when a
non-ISA read/write-styled host
interface type is selected.
ISA I/O Write/
Non-ISA R/W Data
Strobe
1
nIOW/DSTRB
I
The active low nIOW input is
issued by the host to execute I/O
write commands when an ISA
read/write-styled host interface
type is selected (TABLE 3). The
DSTRB input is used to execute
the I/O command when a non-ISA
read/write-styled host interface
type is selected (FIGURE 5).
MISCELLANEOUS (12)



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