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CAM35C44 датащи(PDF) 34 Page - SMSC Corporation |
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CAM35C44 датащи(HTML) 34 Page - SMSC Corporation |
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34 / 50 page ![]() 34 Note: This figure is for illustration purposes only and is not intended to suggest specific implementation details) Registers GPIOA Enable Register The GPIOA Enable register GP00 contains the enable bits for the five general purpose I/O pins (TABLE 31). When any of the GPx_EN bits are “1”, the associated general purpose I/O pin is enabled. When any of the GPx_EN bits are “0”, the associated general purpose I/O pin is disabled. The affects of the GPx_EN bits are summarized in TABLE 30. GP00 can be accessed both in the configuration state and the run state (see section REGISTER ADDRESS MAP on page 16 and TABLE 29). The default value of the GPIOA Enable register after power up is 00H. Bits[7:5] in the GPIOA Enable register are RESERVED. TABLE 31 - GPIOA ENABLE REGISTER D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT GP00 R/W RESERVED GP4_ EN GP3_ EN GP2_ EN GP1_ EN GP0_ EN 0x00 1 0 CLK DQ D-TYPE D Q G TRANS- PARENT GPx_OUT GPx_nIOW GPx_DAT GPx_nIOR GPx_EN GPIOx FIGURE 7 - GENERAL PURPOSE I/O BLOCK DIAGRAM |
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