CAM35C44 datasheet(32/50 Pages) SMSC

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GENERAL PURPOSE I/O

Introduction

The CAM35C44 can support up to 5 general

purpose I/O pins, GPIO[4:0] (TABLE 1).

The

number of available general purpose I/O pins

depends upon the Host Interface Select bits (see

the section MULTIHOST CPU INTERFACE on

page 13).

The general purpose I/O pins are

controlled by the GPIO registers contained in

Bank 1 of the CAM35C44 memory map (see the

section REGISTER ADDRESS MAP on page

16). TABLE 29 summarizes the contents of the

GPIO register bank.

TABLE 29 - GPIO REGISTER BANK MAP

BANK

ADDRESS

DEFAULT

BANK 1

0x00

GPIOA Enable Register

(GPIO)

0x01

0x00

RESERVED

0x02

0x00

GPIOA Data Register

0x03

0x00

RESERVED

0x04

0x00

GPIOA Direction Register

0x05

0x00

RESERVED

0x06

0x00

RESERVED

0x07

0x00

RESERVED

Description

The state of a GPIO pin can be forced to the

value contained its data register, depending on

the state of its direction and enable bits.

For

example, when a GPIO pin is configured as an

output the data register contains a “1” and the

enable bit is active, the GPIO pin will be driven

high. When a GPIO pin is configured as an input

and the enable is active, the value in the data

will

reflect

the

state

the

pin. When a GPIO pin is configured as an input

and the enable is inactive, state changes at the

pin are not reflected in the data register. When

a GPIO pin is configured as an output and the

enable is inactive, changes in the data register

do not affect the pin. TABLE 12 summarizes the

GPIO pin behavior described above. FIGURE 7

illustrates GPIO pin functionality. Note: FIGURE

7 is for illustration purposes only and is not

intended to suggest specific implementation

details.

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