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CAM35C44 датащи(PDF) 14 Page - SMSC Corporation |
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CAM35C44 датащи(HTML) 14 Page - SMSC Corporation |
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14 / 50 page ![]() 14 Host Interface Select The Host Interface Select pins HS[1:0] (TABLE 1) determine the host interface type. The encoding for these bits is shown in TABLE 3. The Host Interface Select pins are static controls and must remain stable during device operation. TABLE 3 - HOST INTERFACE ENCODING HOST INTERFACE SELECT HOST INTERFACE TYPE HS1 HS0 0 0 Reserved 0 1 ISA 1 0 MULTIPLEXED ADDRESS/DATA, Non-ISA Read/Write (FIGURE 5) 1 1 MULTIPLEXED ADDRESS/DATA, ISA Read/Write (FIGURE 4) Host Interface Pin Multiplexing Pin multiplexing for the processor/host interface (TABLE 1) is controlled by the Host Interface Select pins HS[1:0]. ISA signals that are not multiplexed, like IOCHRDY and nNOWS, remain operative regardless of the state of the Host Interface Select bits. The following tables describe processor/host interface multiplexing per pin or per pin group. System Data Bus TABLE 4 - SD[7:0] PIN MULTIPLEXING MUX CONTROLS PIN NAME HS1 HS0 SELECTED FUNCTION SD[7:0] 0 0 NOT DEFINED 0 1 SD[7:0] 1 0 AD[7:0] 1 1 AD[7:0] |
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