CAM35C44 datasheet(16/50 Pages) SMSC

16 / 50 page

and requires a 32-byte memory block. Typically,

address bus and a 1 bit chip select.

TABLE 9 describes the mapping for the four

banks

the

CAM35C44

address

space, CONFIGURATION, GPIO, ACE and

SCE, that are required for device configuration

and run-time control.

The external address pins that are responsible

for register addressing will depend on the Host

Interface Select bits (see section MULTIHOST

CPU INTERFACE on page 13).

TABLE 9 - CAM35C44 REGISTER MAP

8-BYTE

ADDRESS

BANK

SELECT

BITS

ADDRESS RANGE

SA[4:0]

SA4

SA3

0x00 - 0x07

CONFIGURATION

0x08 - 0x0F

GPIO

0x10 - 0x17

ACE

0x18 - 0x1F

SCE

Note

Address Enable (AEN) must be low to access the CAM35C44 registers regardless of the state

of the Host Interface Select bits.

Non-Multiplexed (ISA) Addressing

As shown in TABLE 9 five address bits SA[4:0]

and a chip select nCS are required to access the

CAM35C44 run-time and configuration registers.

In ISA mode, five bits of the ISA System Address

bus

SA[4:0]

determine

the

address,

while

nCS

decodes

the

32-byte

address block.

Note: address block decoding

must be done externally.

The Block Select bits BS[2:0] and two of the

general purpose I/Os GPIO[4:3] are unavailable

in ISA mode.

CAM35C44 датащи(PDF) 16 Page - SMSC Corporation

CAM35C44 датащи(HTML) 16 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

датащи скачать

ссылки URL