MCP19124 datasheet(101/236 Pages) MICROCHIP

101 / 236 page

 2016 Microchip Technology Inc.

DS20005619A-page 101

MCP19124/5

14.0 POWER-DOWN MODE (SLEEP)

Power-Down mode is entered by executing a SLEEP

instruction.

Upon entering Sleep mode, the following conditions

occur:

WDT will be cleared but keeps running, if

enabled for operation during Sleep.

PD bit in the STATUS register is cleared.

TO bit in the STATUS register is set.

CPU clock is disabled.

The ADC is inoperable due to the absence of the

4V LDO power (AVDD) while the ADC Reference

is set to AVDD. To minimize sleep current the

ADC Reference must be set to the default AVDD.

I/O ports maintain the status they had before

SLEEP

was executed (driving high, low or

high-impedance).

Resets other than WDT and BOR are not

affected by Sleep mode.

Analog Circuit power (AVDD) is removed during

Sleep mode.

Refer to individual chapters for more details on

peripheral operation during Sleep.

To minimize current consumption, the following

conditions should be considered:

• Disable both Error Amplifiers by setting bits 1 and

2 in the ABECON Register.

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using Timer1 oscillator

• ADC Reference must be set to the default

condition (AVDD).

•VDR will draw a small amount of current from VDD

when powered from VDD. To eliminate this small

current, disconnect VDR from VDD during Sleep.

• I/O pins that are high-impedance inputs should be

pulled to VDD or GND externally to avoid

switching currents caused by floating inputs.

The SLEEP instruction removes power from the analog

circuitry. AVDD is shut down to minimize current draw in

Sleep mode and to maintain a shutdown current of

50 µA typical. The 5V LDO (VDD) voltage drops to 2.9V

minimum in Sleep mode. External current draw from

the 5V LDO (VDD) should be limited to less than 1mA.

Loads drawing more than 1mA externally during Sleep

mode risk loading down the VDD voltage and tripping

POR.

A POR event during Sleep mode will wake the device

from Sleep. The enable state of the analog circuitry

does not change with the execution of the SLEEP

instruction.

14.1

Wake-Up from Sleep

The device can wake up from Sleep through one of the

following events:

External Reset input on MCLR pin, if enabled

POR Reset

Watchdog Timer, if enabled

Any external interrupt

Interrupts by peripherals capable of running

during Sleep (see individual peripheral for more

information).

The first two events will cause a device reset. The last

three events are considered a continuation of program

execution. To determine whether a device reset or

wake-up event occurred, refer to Section 12.7

“Determining the Cause of a Reset”.

The following peripheral interrupts can wake the device

from Sleep:

Interrupt-on-change

External Interrupt from INT pin

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake up through an interrupt event, the corresponding

interrupt enable bit must be enabled. Wake-up will

occur regardless of the state of the GIE bit. If the GIE

bit is disabled, the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

enabled, the device executes the instruction after the

SLEEP

instruction and will then call the Interrupt

Service Routine. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have an NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

14.1.1

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP

instruction

- SLEEP instruction will execute as a NOP.

- WDT and WDT prescaler will not be cleared.

-TO bit in the STATUS register will not be set.

-PD bit in the STATUS register will not be

cleared.

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