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MCP19124 датащи(PDF) 85 Page - Microchip Technology

номер детали MCP19124
подробное описание детали  Digitally-Enhanced Power Analog Synchronous Low-Side Dual-Loop PWM Controller
PDF  236 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP19124 датащи(HTML) 85 Page - Microchip Technology

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 2016 Microchip Technology Inc.
DS20005619A-page 85
MCP19124/5
12.3
Brown-Out Reset (BOR)
The BOREN bit 8 in the CONFIG register enables or
disables the BOR mode, as defined in the CONFIG
register. A brown-out occurs when VDD falls below
VBOR for greater than 100 µs minimum. On any Reset
(Power-On, Brown-Out, Watchdog Timer, etc.), the
chip will remain in Reset until VDD rises above VBOR
(refer to Figure 12-3). If enabled, the Power-Up Timer
will be invoked by the Reset and will keep the chip in
Reset an additional 64 ms. During power-up, it is
recommended that the BOR configuration bit is
enabled, holding the MCU in Reset (OSC turned off
and no code execution) until VDD exceeds the VBOR
threshold. Users have the option of adding an
additional 64 ms delay by clearing the PWRTE bit. At
this time, the VDD voltage level is high enough to
operate the MCU functions only; all other device
functionality is not operational. This is independent of
the value of VIN, which is typically VDD +VDROPOUT.
During power-down with BOR enabled, the MCU
operation will be held in Reset when VDD falls below the
VBOR threshold. With BOR disabled or while operating
in Sleep mode, the POR will hold the part in Reset
when VDD falls below the VPOR threshold.
FIGURE 12-3:
BROWN-OUT SITUATIONS
Note:
The Power-Up Timer is enabled by the
PWRTE bit in the CONFIG register. If VDD
drops below VBOR while the Power-Up
Timer is running, the chip will go back into
a Brown-Out Reset and the Power-Up
Timer will be re-initialized. Once the VDD
rises above VBOR, the Power-Up Timer
will execute a 64 ms reset.
VDD
Internal
Reset
VDD
VDD
Internal
Reset
Internal
Reset
VBOR
VBOR
VBOR
64 ms(1)
64 ms (1)
64 ms (1)
<64ms
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.



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