MCP19124 datasheet(43/236 Pages) MICROCHIP

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DS20005619A-page 43

MCP19124/5

6.4

Desaturation Detection for

Quasi-Resonant Operation

The MCP19124/5 have been designed with a built-in

desaturation detection comparator module custom

made for quasi-resonant topologies. This is especially

useful for LED-type applications. Through the use of

the

MCP19124/5,

both

synchronous

and

asynchronous quasi-resonant topologies can be

implemented. The DESAT comparator module has the

same features as the UVLO/OVLO and OV comparator

modules, except that it includes some additional

programmable parameters.

The DESATCON register holds the setup control bits

for this module. Common control bits are the polarity

edge

trigger

for

the

interrupt

flag

<CDSINTP><CDSINTN>, comparator output polarity

control CDSPOL, output enable CDSOE and output

status CDSOUT bit. As with the other comparator

modules, the CDSIF is independent of the CDSOE

enable bit. On the front end connected to the DESAT

comparator noninverting input, there is a two-channel

MUX that connects either to the DESATP pin or to the

fixed

internally

generated

band

gap

voltage.

Additionally, the input offset voltage of the DESAT

comparator is factory-trimmed to within ±1 mV typically.

These factory-trimmed values are stored in the

CALWD2 register at address 2081h. Firmware must

read these values into the DSTCAL register (196h). If

more offset is desired, the user can adjust the values

written to the DSTCAL per their implementation.

DESATCON: DESATURATION COMPARATOR CONTROL REGISTER

R/W-0

CDSMUX

CDSWDE

Reserved

CDSPOL

CDSOE

CDSOUT

CDSINTP

CDSINTN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

CDSMUX: DESAT Comparator Module Multiplexer Channel Selection bit

= BG Selected

= DESATP Selected (Default)

bit 6

CDSWDE: DESAT Comparator Watch Dog Enable bit

= Watch Dog signal enables PWM Reset

= Watch Dog signal does not allow PWM reset

bit 5

Reserved

bit 4

CDSPOL: DESAT Comparator Polarity Select bit

= DESAT Comparator output is inverted

= DESAT Comparator output is not inverted

bit 3

CDSOE: DESAT Comparator output enable bit

= DESAT Comparator output PWM is enabled

= DESAT Comparator output PWM is not enabled

bit 2

CDSOUT: DESAT Comparator Output Status bit

If CDSPOL = (inverted polarity)

= CDSVP < CDSVN (DESAT detected)

= CDSVP > CDSVN (DESAT not detected)

If CDSPOL = (noninverted polarity)

= CDSVP > CDSVN (DESAT not detected)

= CDSVP < CDSVN (DESAT detected)

bit 1

CDSINTP: CDSIF Comparator Interrupt on Positive Going Edge Enable bit

= The CDSIF interrupt flag will be set upon a positive going edge

= No CDSIF interrupt flag will be set upon a positive going edge

bit 0

CDSINTN: CDSIF Comparator Interrupt on Negative Going Edge Enable bit

= The CDSIF interrupt flag will be set upon a negative going edge

= No CDSIF interrupt flag will be set upon a negative going edge

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