MCP19124 datasheet(52/236 Pages) MICROCHIP

52 / 236 page

MCP19124/5

DS20005619A-page 52

 2016 Microchip Technology Inc.

6.13

Mode and RFB MUX Control

The MODECON register controls the Master/Slave

configuration.

In Master mode, it allows the VREF2 signal of the

Master MCP19124/5 device to be buffered and

connected to a GPIO pin. This output signal can be

connected to a Slave PWM driver (MCP1631) at the

VREF input to regulate current via the Slave PWM

Controller. Also in Master mode, the CLKOUT sync

signal is routed to GPA1. In Semi-Master Mode users

have the option to implement VREF2 and CLKOUT

independently. In Slave mode the PWM switching

frequency is obtained from the CLKIN pin at GPA1. In

Stand-Alone mode, the VREF2 unity gain buffer is not

connected to a separate GPIO Pin and the PWM

switching frequency is internally generated.

MODECON: MASTER/SLAVE AND RFB MUX CONTROL REGISTER

R/W-0

U-0

R/W-0

U-0

MSC1

MSC0

—

—MSC2

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n = Value at POR

‘1’

= Bit is set

‘0’

= Bit is cleared

bit 7-6

MSC<1:0>: Master/Slave Configuration bits

= Device set as stand-alone unit (VREF2 disabled, switching frequency internally generated)

= Device set as MASTER (VREF2 to GPB1, CLKOUT sync to GPA1)

= Device set as SLAVE MODE (CLKIN switching frequency sync signal to GPA1)

= Device set to SEMI-MASTER MODE

bit 5-4

Unimplemented: Read as ‘0’

bit 3

MSC2: Semi-Master Mode Options bit

= GPB1 is VREF2 Output, GPA1 is general purpose I/O

= GPB1 is general purpose output, GPA1 is CLKOUT

bit 2-0

Unimplemented: Read as ‘0’

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