ML7396AB datasheet(44/140 Pages) LAPIS

44 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

44/140

The following is timing chart for normal mode.

[Conditions]

ADC_CK_SET ([ADC_CLK_SET:B0 0x08(4)])=0b1 (2MHz)

ED_AVG[2:0] ([ED_CNTRL:B0 0x1B(2-0)])=0b011 (ED value 8 times average)

IDLE_WAIT[9:0] ([IDLE_WAIT_L/H:B0 0x17/0x18(1-0)])=0b00_0000_0000 (IDLE detection 0μs)

[IDLE detection case]

CCA_EN

[BUSY detection case]

[Note]

1. After issuing CCA command, transit into no-input state, and exit this state after filter stbilization.

2. When the iput level chnge from no-input to -80dBm, it takes around 32 μs for indicating -80dBm ED value.

ED value

(Internal signal)

CCA_RSLT[1:0]

[CCA_CNTRL:B0 0x15(1-0)]

CCA_DONE

[CCA_CNTRL:B0 0x15(2)]

[CCA_CNTRL:B0 0x15(4)]

ED value[7:0]

[ED_RSLT:B0 0x16]

AD conversion

(16μs)

ED value average period (16μs * 8=128μs)

0b10 (CCA on-going)

ED1

ED3

ED5

ED2

ED6

ED7

Filter stabilization

16 to 32 μs

ED0

●●●

averaging

(0-7)

< CCA_TH_LV

B0 0x13

0b00 (IDLE)

IDLE_WIAT[9:0]

should be set, for

IDLE detection for

longer period

CCA execution time (Max. 32μs+128μs=160μs)

CCA_EN

ED value

(Internal signal)

CCA_RSLT[1:0]

[CCA_CNTRL:B0 0x15(1-0)]

CCA_DONE

[CCA_CNTRL:B0 0x15(2)]

[CCA_CNTRL:B0 0x15(4)]

ED Value[7:0]

[ED_RSLT:B0 0x16]

AD conversion

(16μs)

ED value averaging (16μs * 8=128μs)

0b10 (CCA on-going)

ED1

ED3

ED5

ED2

ED6

ED7

Filter stabilization

16 to 32 μs

ED0

●●●

averaging

(0-7)

> CCA_TH_LV

B0 0x13

0b01 (BUSY)

IDLE_WIAT[9:0]

should be set, for

IDLE detection for

longer period

CCA execution time (Max. 32μs+128μs=160μs)

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