ML7396AB datasheet(98/140 Pages) LAPIS

98 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

98/140

●RX mode (Packet mode, packet length ≤ 256 bytes)

Packet mode can be selected setting DIO_EN ([PLL_MON/DIO_SEL:B0 0x69(1)]) =0b0. In DIO mode, when issuing

RX_ON command, preamble and SFD detection will be started. After preamble and SFD are detected, RX data will be stored

into a FIFO. After RX completion interrupt (INT[18]/[19] group3) occurs, the host MCU will read RX data from

[RD_RX_FIFO:B0 0x7F] register. If CRC error interrupt (INT[20]/[21]) is generated, FIFO data has to be cleared by setting

(FIFO_CLR1/0 ([INT_SOURCE_GRP1:B0 0x26(7/6)]) =0b0. After clearing RX retaive interrpts, if receiving the next packet,

maintain RX_ON status and waiting for next RX completion interrupt. If TX is expected after RX, TX_ON should be issued by

[RF_STATUS:B0 0x6E] register. If terminating RX, issuing TRX_OFF by [RF_STATUS:B0 0x6E] register.

If FIFO-Full trigger and FIFO-Empty trigger are not used, please set 0x00 to both [RX_ALARM_LH:B0 0x37]) and

[RX_ALARM_HL:B0 0x38)] registers.

START

RX FIFO trigger level setting

[RX_ALARM_LH:B0 0x37] =0x00

[RX_ALARM_HL:B0 0x38] =0x00

RX_ON issue

[RF_STATUS:B0 0x6C]

From automatic ACK receive in TX mode

[Note]

If CRC_EN ([FEC/CRC_SET:B0

0x46(3)])=0b0, read out all RX

data from a FIFO before issuing

TRX_OFF command.

Please refer [FEC/CRC_SET:B0

0x46] register

Yes

Set ACK_STOP =0b1

[AUTO_ACK_SET:B0 0x55(0)

]

RX completion (INT[18]/[19])?

[INT_SOURCE_GRP3:B0 0x26]

Yes

Go to CRC error flowchart

in “Error process”

CRC error (INT[20]/INT[21])?

[INT_SOURCE_GRP3:B0 0x26]

AUTO_RX_EN=0b1?

[AUTO_ACK_SET] B0 0x55

Read RX data from FIFO

Set ACK_STOP =0b0

[RD_RX_FIFO:B0 0x7F]

[AUTO_ACK_SET:B0 0x55(0)

]

Yes

Go to Act TX mode flowchart

ACK request?

(≤256byte)

Yes

END

TX?

TRX_OFF issue

[RF_STATUS:B0 0x6C]

Clear interrupts

INT[18],[20] or INT[19].[21]

[INT_SOURCE_GRP3:B0 0x26]

Next packet RX?

Go to TX flowchart

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