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ML7396AB датащи(PDF) 7 Page - LAPIS Semiconductor Co., Ltd.

номер детали ML7396AB
подробное описание детали  Sub GHz band short range wireless transceiver IC
PDF  140 Pages
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производитель  LAPIS [LAPIS Semiconductor Co., Ltd.]
домашняя страница  http://www.lapis-semi.com/
Logo LAPIS - LAPIS Semiconductor Co., Ltd.

ML7396AB датащи(HTML) 7 Page - LAPIS Semiconductor Co., Ltd.

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PIN DEFINITION(continued)
●Miscellaneous pins
Pin
No
Pin name
Reset
state
I/O
Active
Level
Detail function
7
RESETN
I
Is
L
Hardware reset
L: Hardware reset enable
H: normal operation
4
XIN
I
Ios
P or N
36MHz crystal pin1
*Fixed to GND in case of using external
clock
5
XOUT
O
Oos
P or N
36MHzcristal pin2
*Fixed to GND in case of using external
clock
6
TCXO
I
IA
-
External clock (TCXO) input pin.
*Fixed to GND in case of using crystal
oscillator
20
ANT_SW
O/L
O
H or L or
OD
Diversity control signal
21
TRX_SW
O/L
O
H or L or
OD
TX-RX switch signal
19
TEST
I
I
H
Test mode input
Fixed to “L” for normal use
17
DMON*1
O
O
H
Digital monitor pin
Primary function: Clock output (6MHz)
Secondary function: PLL_LD output
Third function: FIFO trigger output
22
DCNT
O/L
O
H or L or
OD
External TX PA control signal
31,35
N.C.
-
-
-
Non connection
[Description]
*1 Function of DMON pin can be selected by following condition. Clock output as a default.
If clock output is not used, please select another function. Please refer to each register description for more details.
Primary function will have higher priority when multiple function are configured simultaneously.
Configuration of DMON output
Function Name
Configuration register name
Address
Bit position (bit symbol)
CLK output
CLK_SET
B0 0x02
bit4 (CLKOUT_EN)
PLL_LD output
PLL_MON/DIO_SEL
B0 0x69
bit4 (PLL_LD)
FIFO trigger output
CRC_AREA/FIFO_TRG
B0 0x77
bit0 (FIFO_TRG_EN)



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