ML7396AB datasheet(40/140 Pages) LAPIS

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FEDL7396A/B/E-07

ML7396A/B/E

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In the above setting, If INV_ANT_SW([2DIV_CTRL: B0 0x71(3)])=0b1, ANT_CTRL1([2DIV_CTRL: B0 0x71(5)])=0b1

are set, polarity of ANT_SW pin (#20)is reversed.

INV_ANT_SW=0b0

ANT_CTRL1=any

(default setting)

INV_ANT_SW=0b1

ANT_CTRL1=0b1

TX/RX state

ANT_SW

TRX_SW

ANT_SW

TRX_SW

Description

Idle

Idle state

TX state

When diversity disable or intial codition when

diversity enable is set ([2DIV_CTRL: B0

0x71(0)]=0b1).

H/L

L/H

If diversity enable is set, during searching

(ANT_SW=H) and (ANT_SW=L) is switched

alternatively. After diversity completion, fix to

one of the condition.

Antenna switch forced setting

ANT_SW pin (#20) and TRX_SW pin (#21) output conditions can be set to fix by [RF_CNTRL_SET: B0 0x75] register, or

2DIV_RSLT2 ([2DIV_RSLT:B0 0x72(1)]) and INV_TRX_SW ([2DIV_CNTRL:B0 0x71(2)]) when diversity fuction is

diabled.

1. Forced setting by [RF_CNTRL_SET] register

ANT_SW pin: By ANT_SW_EN (bit1)=0b1, ANT_SW_SET (bit5) condition will be output.

TRX_SW pin: By TRX_SW_EN (bit0)=0b1, TRX_SW_SET (bit4) condition will be output.

2. Forced setting by 2DIV_RSLT2 bit and INV_TRX_SW bit when diversity function is disabled

( 2DIV_EN ([2DIV_CNTRL:B0 0x71(0)])=0b0)

ANT_SW pin: When 2DIV_RSLT2=0b0, output “L”. When 0b1, output “H”.

TRX_SW pin: When INV_TRX_SW=0b0, output “L”. When 0b1, output “H”.

Output defined by [RF_CNTRL_SET:B0 0x75] registers setting has higer priority.

When diversity is enable (2DIV_EN=0b1), output definced by 2DIV_RSLT2 and INV_TRX_SW are ignored.

Any antenna switch setting is inhibited to avoid out-of-synchronization during RECEIVE state.

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