ML7344CE datasheet(46/154 Pages) LAPIS

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FEDL7344C/E/J-05

ML7344C/E/J

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●FIFO control function

ML7344 has on-chip TX_FIFO(64Byte) and RX_FIFO(64Byte). As TX/RX_FIFO do not support multiple

packets, packet should be processed one by one. If RX_FIFO keeps RX packet and next RX packet is received,

RX_FIFO will be overwritten. It applies to TX_FIFO as well. However TX FIFO access error interrupt

(INT[20] group3) will be generated. When receiving, RX data is stored in FIFO (byte by byte) and the host

MCU will read RX data through SPI. When transmitting, host MCU write TX data to TX_FIFO through SPI

and transmitting through RF.

Writing or reading to FIFO is through SPI with burst access. TX data is written to [WR_TX_FIFO: B0 0x7C]

counter automatically. If FIFO access is suspended during write or read operation, address will be kept until the

packet will be process again. Therefore, when resuming FIFO access, next data will be resumed from the

suspended address.

FIFO control register are as follows:

Function

TX FIFO Full level setting

[TXFIFO_THRH: B0 0x17]

TX FIFO Empty level setting

[TXFIFO_THRL: B0 0x18]

RX FIFO Full level setting

[RXFIFO_THRH: B0 0x19]

RX FIFO Empty level setting

[RXFIFO_THRL: B0 0x1A]

FIFO readout setting

[FIFO_SET: B0 0x78]

RX FIFO data usage status indication

[RX_FIFO_LAST: B0 0x79]

TX packet Length setting

[TX_PKT_LEN_H/L: B0 0x7A/7B]

RX packet Length setting

[RX_PKT_LEN_H/L: B0 0x7D/7E]

TX FIFO

[WR_TX_FIFO: B0 0x7C]

FIFO read

[RD_FIFO: B0 0x7F]

[TX]

TX data L-field value is set to [TX_PKT_LEN_H: B0 0x7A], [TX_PKT_LEN_L: B0 0x7B] register. If

Length is 1 byte, [TX_PKT_LEN_L] register will be transmitted.

Length can be set to LENGTH_MODE([PKT_CTRL2: B0 0x05(0)]).

ii)

TX data is written to [WR_TX_FIFO:B0 0x7C] register.

NOTE:

If TX_FIFO write sequence is aborted during transmission, STATE_CLR0 [STATE_CLR:B0 0x16(0)]

(TX FIFO pointer clear) must be issued. Otherwise data pointer is kept in the LSI and the next packet is

not processed properly.

For example, TX FIFO access error interrupt (INT[20] group3) is generated. This interrupt can be

generated when the next packet data is writren to the TX_FIFO before transmitting previous packet data or

FIFO overrun (FIFO is written when no TX_FIFO space) or underrun (attempt to transmit when TX_FIFO

is empty)

Depending on the packet format, TX data Length value is different.

Format A: Length includs data area excluding L-field and CRC data.

Format B: Length includes data area excluding L-field.

Format C: Length includes data area excluding L-field.

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