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ML7344CE датащи(PDF) 95 Page - LAPIS Semiconductor Co., Ltd. |
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ML7344CE датащи(HTML) 95 Page - LAPIS Semiconductor Co., Ltd. |
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95 / 154 page ![]() FEDL7344C/E/J-05 ML7344C/E/J 95/154 ●I/Q adjustment Image rejection ratio can be adjusted by tuning IQ signal balance. The adjustment procedure is as follows: 1. From SG, image frequency signal is input to ANT pin (#24). Input signal: no modulation wave Input frequency: channel frequency - (2 * IF frequency) IF frequency = 200kHz: Input level: -70dBm 2. Isuuing RX_ON by [RF_STATUS:B0 0x0b] register, by adjusting [LO_BIAS_IP: B2 0x2C]、From 0x50 To 0xD0 Step 0x04 [LO_BIAS_IN: B2 0x2D]、From 0x60 To 0xA0 Step 0x10 [LO_BIAS_QP: B2 0x2E]、From 0x50 To 0xD0 Step 0x04 [LO_BIAS_QN: B2 0x2F]、From 0x60 To 0xA0 Step 0x10 , finding setting value so that ED value [ED_RSLT: B0 0x3A] is minimum. 3. It is possible to choice the adjusted value and break the above search flow at halfway. To obtain minimum 30dB blocking characteristic for image frequency, ML7344 requires more than 40dB attenuation for image frequency (IMRR: IMage Rejection Ratio). The 10dB differ is caused by co-channel blocking characteristic of ML7344. Because input -70dBm signal during IQ adjustment, IMRR is more than 40dB if ML7344 indicates less than -110dBm by ED value. It is possible to break adjustment flow at halfway by using the ED value as “Target value” in the IQ adjustment flow. ●IQ adjustment flow For IQ adjustment, using Bank2 (closed Bank) registers. Any other register access is inhibited. 1 Read ED value [ED_RSLT: B0 0x3A] IQ Bias initializing setting [LO_BIAS_IN: B2 0x2D] = 0x80 [LO_BIAS_QN:B2 0x2F] = 0x80 START Power on SG output setting modulation: no modulation level : -70dBm frequency: CH frequency- 2 * IF frequency Initialize setting * Please refer to “Initialization table”. RX_ON setting [RF_STATUS: B0 0x0B] 1 IQ adjustment by following register [LO_BIAS_IP: B2 0x2C] [LO_BIAS_QP:B2 0x2E] Read ED value < Target value ? Change setting value of [LO_BIAS_IN: B2 0x2C] [LO_BIAS_QN:B2 0x2E] No |
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