ST92196A datasheet(161/268 Pages) STMICROELECTRONICS

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- CLOSED CAPTION DATA SLICER (DS)

DATA SLICER (Cont’d)

8.6.3 Data Slicer Operation

The data slicer is enabled or disabled using the

EDS bit in the DR1 register. The Data Slicer clock

frequencies are generated by the clock generator

starting from a basic 4 MHz clock.

The decoder is activated when the output of a half-

line counter matches the value written by the user

in the CR1 register and a horizontal sync pulse is

detected while the match is valid. Odd values of

half-line counts in register CR1 are used to decode

lines in Field#1, even values to decode lines in

Field#2. The CC decoder includes logic for recog-

nizing the current field and generates a corre-

sponding FIELD1 signal.

The slicing level is automatically adjusted during

the clock run-in window to obtain approximately a

50% duty cycle waveform corresponding to the

clock run-in signal at the data slicer output. Refer

to Figure 68.

DSOUT is fed into the data processor where it is

processed for the selected line. The waveforms of

DSOUT at the output of the comparator for signals

received in either closed caption or Gemstar for-

mat are shown in Figure 68. The closed caption

signal starts with 7 cycles of clock run-in signal

with a frequency of about 500KHz, and ends with

16 bits (2 bytes) of data where each bit has a peri-

od of approximately 2µs. The Gemstar signal has

only 5 cycles of the 500KHz clock run-in signal and

transmits 32 bits (4 bytes) of data with the period

of each bit reduced to about 1µs.

Closed caption and Gemstar signals are detected

by looking for their distinctive frame codes. “Frame

code” refers to the characteristic of the signal

waveform in a time interval between the clock run-

in and data sections of the signal as shown in Fig-

ure 68. The frame code detector examines during

a 5µs window selected outputs of a 32-stage shift

DSOUT obtained with a 4MHz clock at.25µs inter-

vals. In normal operation the frame code detector

requires the 5 bits marked with an upward pointing

arrow (^) to be correct, but in a search mode cov-

ering all lines in the vertical blanking interval all 8

bits of the frame code are examined by when the

SEARCH control bit in the CR2 register is set.

Identification of the frame code results in setting

either the CCMODE or GSMODE bit in the MR

ing 2 or 4 data bytes is activated in correct phase

relative to the data signal. Parity of all data bytes is

checked and appropriate flags EVNP[4:1] are set

correspondingly in the MR register.

An interrupt is always generated at the end of the

specified line and on the corresponding line of the

opposite field, even if no data has been recovered.

The Data Slicer is able to recover data from 2 or

more adjacent lines. However, except for the last

line to be decoded in the current field, in such a sit-

uation recovered data bytes must be read out with-

in a time period of 18µs after an interrupt has oc-

curred.

During normal operation, the interrupt should oc-

cur at the end of the selected line. However, if data

must be recovered from adjacent lines in the same

field, then it becomes necessary for some of the

lines to generate an interrupt at the leading edge

of interrupt signal, and thereafter for the same line

at the trailing edge of the interrupt signal. The

IRQ_INV bit in the CR1 Register controls the po-

larity of the interrupt signal. The TED0 bit in the

EITR register should be set to “1” and INV_IRQ

should be used to control the data slicer interrupt

polarity.

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