ST92196A datasheet(165/268 Pages) STMICROELECTRONICS

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- CLOSED CAPTION DATA SLICER (DS)

DATA SLICER (Cont’d)

DATA REGISTER 4 (DR4)

R243 - Read only

Reset Value: 0000 0000 (00h)

Bit 7:0 = D4[7:0]:

Fourth data byte for Gemstar,

second data byte for closed caption

CONTROL REGISTER 1 (CR1)

R244 - Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = STNDBY: Standby mode

This bit selects the standby mode (operation when

main power supplies have been turned off).

0: The horizontal deflection pulses (HPLS) are

used for synchronization

1: Horizontal synchronization pulses are internally

generated from the incoming video signal (verti-

cal synchronization signal for the Data Slicer is

always derived from incoming video).

Bit 6 = IRQ_INV:

Interrupt Signal Polarity.

This bit is set and cleared by software. It controls

the position of the data slicer’s interrupt signal to

the µP (CCIRQ) to be on the rising or falling edge

of the slicers interrupt signal (IRQ). Refer to Figure

68. It is used to setup the interrupt to occur at the

beginning of the specified line or at the end of the

line.

0: The interrupt request occurs at the end of the

specified line

1: The interrupt request occurs at the beginning of

the specified line.

Note: Data recovery from adjacent lines:

In situations where closed caption or Gemstar

data has to be recovered from adjacent lines, e.g.

from Line#20 and Line#21 in Field#1, it becomes

necessary to generate an interrupt both at the ris-

ing edge as well as at the falling edge of the IRQ

signal shown in Figure 68. The interrupt at the ris-

ing edge of IRQ for Line#20 is obtained by setting

the IRQ_INV bit and writing the LN[5:0] value for

Line#21 in the CR1 Register. Usually it will be too

late to write this value at the end of Line#20. After

the LN[5:0] value for Line#21 has been written, the

software must also clear the IRQ_INV bit before

exiting the interrupt routine. This will cause the

next interrupt to be generated at the falling edge of

IRQ which occurs at the end of Line#20. At this

time the character codes transmitted in Line#20

are available for reading.

Bit 5:0 = LN[5:0]:

Closed caption line selector.

The data slicer current half-line count is compared

with the LN[5:0] value; the half-line counter is re-

leased from the reset state when the first vertical

sync pulse is detected. With the NTSC standard,

to select line “N” the LN[5:0] value must be set to

LN[5:0] = [(2*N)-9] for Field#1, and [(2*N)-8] for

Field#2.

Examples: LN[5:0] = 33 (21hex) for Line#21 in

Field 1, LN[5:0] = 34 (22hex) for Line#21 in Field 2.

CONTROL REGISTER 2 (CR2)

R245 - Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = EDS:

Enable Data Slicer.

This bit is set and cleared by software.

0: Disable Data Slicer (analog part)

1: Enable Data Slicer

Bit 6 = IRFL:

Interrupt Flag.

This bit is set by hardware, when an interrupt re-

quest is issued. It must be cleared by software

when the corresponding interrupt service routine

has been finished. A ‘clear’ can be performed by

any write operation to this register.

0: No Data Slicer interrupt pending

1: Data Slicer interrupt pending

Bit 5 = CCID:

External Interrupt Source Selection.

This bit is set and cleared by software.

0: The interrupt request from the Data Slicer is for-

warded to the CPU

1: The interrupt from the external interrupt pin is

forwarded to the CPU.

D4.7 D4.6 D4.5 D4.4 D4.3 D4.2 D4.1 D4.0

STND

IRQ_

INV

LN5 LN4

LN3 LN2

LN1 LN0

EDS IRFL CCID

SEA

RCH

SCG

_EN

PHD

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