ST92196A datasheet(59/268 Pages) STMICROELECTRONICS

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ON-CHIP DIRECT MEMORY ACCESS (DMA)

4 ON-CHIP DIRECT MEMORY ACCESS (DMA)

4.1 INTRODUCTION

The ST9 includes on-chip Direct Memory Access

(DMA) in order to provide high-speed data transfer

between peripherals and memory or Register File.

Multi-channel DMA is fully supported by peripher-

als having their own controller and DMA chan-

nel(s). Each DMA channel transfers data to or

from contiguous locations in the Register File, or in

Memory. The maximum number of bytes that can

be transferred per transaction by each DMA chan-

nel is 222 with the Register File, or 65536 with

Memory.

The DMA controller in the Peripheral uses an indi-

rect addressing mechanism to DMA Pointers and

Counter Registers stored in the Register File. This

is the reason why the maximum number of trans-

actions for the Register File is 222, since two Reg-

isters are allocated for the Pointer and Counter.

counters in order to offer the full 65536 byte and

count capability.

4.2 DMA PRIORITY LEVELS

The 8 priority levels used for interrupts are also

used to prioritize the DMA requests, which are ar-

bitrated in the same arbitration phase as interrupt

requests. If the event occurrence requires a DMA

transaction, this will take place at the end of the

current instruction execution. When an interrupt

and a DMA request occur simultaneously, on the

same priority level, the DMA request is serviced

before the interrupt.

An interrupt priority request must be strictly higher

than the CPL value in order to be acknowledged,

whereas, for a DMA transaction request, it must be

equal to or higher than the CPL value in order to

be executed. Thus only DMA transaction requests

can be acknowledged when the CPL=0.

DMA requests do not modify the CPL value, since

the DMA transaction is not interruptable.

Figure 25. DMA Data Transfer

PERIPHERAL

VR001834

DATA

ADDRESS

COUNTER

TRANSFERRED

MEMORY

START ADDRESS

COUNTER VALUE

DATA

GROUP F

PERIPHERAL

PAGED

REGISTERS

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