ST92196A datasheet(158/268 Pages) STMICROELECTRONICS

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- ON SCREEN DISPLAY CONTROLLER (OSD)

OSD CONTROLLER (Cont’d)

SCAN LINE REGISTER (OSDSLR)

R251 - Read Only

Reset Value: xxxx xxxx (xxh)

Bits 7:0 = SL[7:0]

Scan Line Counter Value

These bits indicate the current vertical position of

the TV beam.

The most significant bit SL8 of this counter is locat-

ed in the Flag Bit register OSDFBR (see below).

This counter starts from 0 at the top of the screen

(i.e. after the Vsync pulse) and is incremented by

HSYNC.

MUTE REGISTER (OSDMR)

R252 - Read/Write

Reset Value: 00xx x000

Bit 7 = ADMULT

Address Multiply control bit

This bit, together with the ODEVN bit, controls the,

OSDRAM address generation. (Refer to the note

below for more details)

0: The CPU address is used to address the OS-

DRAM, i.e. the CPU address LSB bit is used as

OSDRAM address LSB.

1: The CPU address is multiplied by 2 and the

ODEVN control bit is used as the OSDRAM LSB

address bit.

Note: This mechanism is intended for improved

software compatibility with the ST9296 when the

Display works in basic parallel mode; it allows to

do a buffer transfer to the OSDRAM using a basic

"ld memory-to-memory with post-increment" in-

struction; i.e.: ld(..)+, ('')+ to fill up the row buffer,

making an automatic reservation for the attribute

byte associated with the character.

Bit 6 = ODEVN

Odd/Even address control bit

This bit controls the OSDRAM address LSB bit

when the ADMULT bit is high.

Refer to the ADMULT bit description for further de-

tails.

Bits 5:3 are reserved

Bits 2:0 = LSM[2:0]

Line Start Mute value

These bits are used to program the mute duration

after the beginning of each TV line.

When the Display works in 1H mode the mute du-

ration can be adjusted in 2µs steps from 2 to 14 µs.

When the Display works in 2H mode the mute du-

ration can be adjusted in 1µs steps from 1 to 7 µs.

The LSM bits also define the HSY flag duration.

The Mute duration is expressed by the following

equation (the “1µs” is a frequency issued from the

crystal oscillator):

for 2H display mode: Tmute = LSM[2:0] * (1 µs)

for 1H display mode: Tmute = LSM[2:0] * 2*(1 µs)

in both 1H/2H modes, if LSM[2:0] = 0 then Tmute =

Hsync width.

SL7

SL6

SL5

SL4

SL3

SL2

SL1

SL0

ADMULT ODEVN

LSM2

LSM1 LSM0

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