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ST92196A датащи(PDF) 160 Page - STMicroelectronics

номер детали ST92196A
подробное описание детали  8/16-BIT MCU FOR TV APPLICATIONS WITH UP TO 96K ROM, ON-SCREEN-DISPLAY AND 1 OR 2 DATA SLICERS
PDF  268 Pages
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- CLOSED CAPTION DATA SLICER (DS)
8.6 CLOSED CAPTION DATA SLICER (DS)
8.6.1 Introduction
Depending on the ST9 device, one or two Data
Slicers may be available in the MCU (refer the de-
vice feature list and Register map).
Each Data Slicer can extract either
s
Closed caption data from a composite video
signal broadcast in the EIA-608 format. Used in
conjunction with the OSD, it allows closed
caption information to be displayed on a TV
screen.
s
Gemstar format data transmitted on one or more
horizontal lines in the vertical blanking interval.
In this format, one line contains 4 bytes of data.
The Data Slicer automatically determines the data
format in the specified line and sets the appropri-
ate flag.
8.6.2 Functional Description
Inputs
CCVIDEO: Composite video signal AC coupled
through a 1µF capacitor.
HSYNC:
Horizontal deflection pulse.
VSYNC:
Vertical deflection pulse.
F_4MHz:
4 MHz clock from frequency
multiplier.
Outputs
IRQ:
Conditional negative edge interrupt
request, connected to a CPU
interrupt channel (See Interrupts
Chapter).
As shown in Figure 67, the Data Slicer accepts the
incoming composite video as an AC coupled sig-
nal through a 1µF capacitor to the CCVIDEO pin.
The OSD synchronization signals and a 4 MHz
crystal derived clock are used in the data slicer
signal extraction logic.
Data extraction can be programmed for a selecta-
ble line in either field for a video signal of ampli-
tude of 2V +/-3dB. The slicing level for data is con-
trolled automatically by hardware.
The output signal DSOUT is high when the input
signal exceeds the level of the reference voltage
Vslice, and low when it is less than Vslice.
The clamp is disabled from the time of detection of
vertical sync in CCVIDEO (a sync pulse wider than
12µs) up to line 28.
Note: For good slicing results, it is advised to set
VDDA >= 5.3V. Remember also that VDDA < VDD
+ 0.3V.
Figure 67. Block Diagram
-
+
-
+
-
+
DATA
PROCESSOR
UP/DOWN
COUNTER
DATA
REGISTERS
STATUS
REGISTER
CLOCK
GENERATOR
CLAMP
Interrupt
4 MHz
(from Frequency Multiplier)
CSYNC
Vref (Black)
Vref (Sync)
CCVIDEO
1µF
Vslice
Vref



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