ST92196A datasheet(157/268 Pages) STMICROELECTRONICS

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- ON SCREEN DISPLAY CONTROLLER (OSD)

OSD CONTROLLER (Cont’d)

FLAG BIT REGISTER (OSDFBR)

R250 - Read/Write

Reset Value: xxxx xxxx (xxh)

Bit 7 = BUFL

Buffer Flag bit

This bit indicates which Row Buffer of the OSD

RAM is being used by the Display.

The BUFL flag is automatically re-evaluated each

time the Scan & Event line matching condition is

fulfilled. In case the “TE” bit is reset (see the OS-

DER register), the “BUFL” flag remains un-

changed as NO row buffer change occurs.

0: The OSD displays the content of the second row

buffer (the one NOT pointed by the “first buffer

start address” value).

1: The OSD displays the content of the Row Buffer

location pointed by the “first buffer start address”

value.

Note: The BUFL flag is automatically reset when

the (DION,OSDE) bits are switching from any oth-

er value to (1,1); it will be set at the first Buffer

transfer (scan & event match and TE=1).

Bit 6 = VSY

Vsync status bit

This bit gives the status of the VSYNC input signal.

0: the VSYNC input signal is inactive.

1: the VSYNC input signal is active.

Note: The VSYNC signal polarity is compensated

to always provide VSY=1 during the vertical pulse.

Bit 5 = HSY

Hsync status bit

This bit gives the status of the internal HS signal

generated by the skew corrector and locked to the

external HSYNC signal.

0: The HS signal is inactive.

1: The HS signal is active.

Note: the HSYNC signal polarity is compensated

to provide HSY=1 during the horizontal pulse.

Note: HSY remains active during the whole “Line

Start Mute” timing which is software controlled

through both the DBLS bit and the LSM[2:0] value

(see OSDER and OSDMR registers).

Bit 4 = VSDL

Delayed Vertical Pulse status bit

This bit indicates the status of the VDPLS internal

signal (it is the delayed vertical pulse issued from

the programmable vertical delay unit as described

by the OSDDR register bits VD[3:0])

0: The VDPLS internal signal is inactive

1: The VDPLS internal signal is active

Note: the VDPLS signal polarity is compensated

to provide VSDL =1 during the vertical pulse.

Bit 3 = FIELD

Field status bit

This bit indicates the current TV field.

0: TV beam is in field 2 (even field)

1: TV beam is in field 1 (odd field)

Bit 2 = DINT

Display Interrupt flag bit

This bit is set by hardware when an OSD interrupt

occurs. This bit must be reset by Software. Refer

to Table 32.

Table 32. Display and Mouse Interrupt Flags

Note: To handle OSD interrupts, it is recommend-

ed to clear the pending bit associated with the ex-

ternal interrupt channel used for the OSD (see the

chapter on Interrupts) and then poll the two flag

bits (DINT & MOIT) in series within the Display in-

terrupt routine.

Bit 1 = MOIT

Mouse pointer Interrupt flag.

This bit indicates which is the source of the OSD

interrupt (See Table 32). This bit must be reset by

Software.

Bit 0 = SL8

Most Significant Bit of the Scan Line

counter

Refer to the description of the OSDSLR register.

BUFL

VSY

HSY

VSDL

FIELD

DINT

MOIT

SL8

DINT

MOIT

Meaning

No Interrupt

Mouse Interrupt

Display Interrupt

Mouse and Dis-

play Interrupts

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