UCD3138ARMHT datasheet(46/87 Pages) TI1

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ADC

Channels

S/H

12-bit SAR

ADC

12-bit SAR

ADC

ADC12 Block

ADC12

Control

ADC Channel

ADC

Averaging

Digital

Comparators

DPWM

Modules

ADC12 Registers

Analog

Comparators

ADC External Trigger (from pin)

UCD3138A

SLUSC66C – MARCH 2015 – REVISED SEPTEMBER 2016

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Detailed Description

Figure 7-14. ADC12 Control Block Diagram

7.5.5.4

Timers

External to the Digital Power Peripherals there are 3 different types of timers in UCD3138A . They are the

24-bit timer, 16-bit timer and the Watchdog timer

7.5.5.4.1 24-bit PWM Timer

There is one 24 bit counter PWM timer which runs off the Interface Clock and can further be divided down

by an 8-bit pre-scalar to generate a slower PWM time period. The timer has two compare registers (Data

Registers) for generating the PWM set/unset events. Additionally, the timer has a shadow register (Data

Buffer register) which can be used to store CPU updates of the compare events while still using the timer.

The selected shadow register update mode happens after the compare event matches.

The two capture pins TCMP0 and TCMP1 are inputs for recording a capture event. A capture event can

be set either to rising, falling, or both edges of the capture pin. Upon this event, the counter value is stored

in the corresponding capture data register.

The counter reset can be configured to happen on a counter roll over, a compare equal event, or by

software controlled register. Five interruptions from the PWM timer can be set, which are the counter

rollover event (overflow), either capture event 0 or 1, or the two comparison match events. Each interrupt

can be disabled or enabled.

Upon an event comparison on only the second event, the TCMP pin can be configured to set, clear, toggle

or have no action at the output. The value of PWM pin output can be read for status or simply configured

as general purpose I/O for reading the value of the input at the pin. The first compare event can only be

used as an interrupt.

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