UCD3138ARMHT datasheet(19/87 Pages) TI1

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Error ADC

(Front End)

Filter

Digital

PWM

EAP

EAN

DPWMA

DPWMB

UCD3138A

www.ti.com

SLUSC66C – MARCH 2015 – REVISED SEPTEMBER 2016

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Specifications

5.7

Peripherals

5.7.1

Digital Power Peripherals (DPPs)

At the core of the UCD3138A controller are three DDPs. Each DPP can be configured to drive from one to

eight DPWM outputs. Each DPP consists of:

•

Differential input error ADC (EADC) with sophisticated controls

•

Hardware accelerated digital 2-pole/2-zero PID based compensator

•

Digital PWM module with support for a variety of topologies

These can be connected in many different combinations, with multiple filters and DPWMs. They are

capable of supporting functions like input voltage feed forward, current mode control, and constant

current/constant power, and so on. The simplest configuration is shown in the following figure:

5.7.1.1

Front End

Figure 5-3 shows the block diagram of the front end module. It consists of a differential amplifier, an

adjustable gain error amplifier, a high speed flash analog-to-digital converter (EADC), digital averaging

filters and a precision high resolution set point DAC reference. The programmable gain amplifier in concert

with the EADC and the adjustable digital gain on the EADC output work together to provide 9 bits of range

with 6 bits of resolution on the EADC output. The output of the Front End module is a 9-bit sign extended

result with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output

could be either 1, 2, 4 or 8 LSBs. In addition each EADC has the ability to automatically select the AFE

value such that the minimum resolution is maintained that still allows the voltage to fit within the range of

the measurement. The EADC control logic receives the sample request from the DPWM module for

initiating an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the

digital compensator for processing of the representative error. The set point DAC has 10 bits with an

additional 4 bits of dithering resulting in an effective resolution of 14 bits. This DAC can be driven from a

variety of sources to facilitate things like soft start, nested loops, and so on. Some additional features

include the ability to change the polarity of the error measurement and an absolute value mode which

automatically adds the DAC value to the error.

It is possible to operate the controller in a peak current mode control configuration; an EADC is

recommended for implementing peak current mode control. In this mode, topologies like a phase shifted

full bridge converter can be controlled to maintain transformer flux balance. The internal DAC can be

ramped at a synchronously controlled slew rate to achieve a programmable slope compensation. This

eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward performance. A0 is

a unity gain buffer used to isolate the peak current mode comparator. The offset of this buffer is specified

in Section 5.5.

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