UCD3138ARMHT datasheet(16/87 Pages) TI1

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UCD3138A

SLUSC66C – MARCH 2015 – REVISED SEPTEMBER 2016

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Specifications

Electrical Characteristics (continued)

3 V

≤ VV33A = VV33D = VV33DIO ≤ to 3.6 V, 1 μF of capacitance from BP18 to DGND, –40°C ≤ TJ ≤ 125°C (unless otherwise

noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

(2)

Minimum and maximum values are specified by design and characterization data.

(3)

DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.

(4)

On the 40-pin package V33DIO is connected to V33D internally.

(5)

The maximum total current, IOH(max) and IOL(max) for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop

specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH.

(6)

Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which

has no variation associated with it, must be accounted for when calculating the system dynamic response.

ADC12 INL integral nonlinearity, end

point(2) (See Figure 6-1)

ADC_SAMPLINGSEL = 0 to 6 for all

ADC12 data

–3.9

±2

4.5

LSB

ADC12 INL integral nonlinearity, best

fit(2) (See Figure 6-1)

–2.3

±1.5

2.6

LSB

ADC12 DNL differential nonlinearity(2)

–0.8/+2.4

LSB

ADC Zero Scale Error

–7

ADC Full Scale Error

–35

Input bias

VADC12 = 2.5 V

400

Input leakage resistance(1)

ADC_SAMPLINGSEL = 0 or

ADC_SAMPLINGSEL = 6

Ω

Input Capacitance(1)

ADC single sample conversion time(1)

ADC_SAMPLINGSEL = 0 or

ADC_SAMPLINGSEL = 6

3.9

μs

DIGITAL INPUTS/OUTPUTS(3)(4)

VOL

Low-level output voltage(5)

IOH = 4 mA, VV33DIO = 3 V

DGND

+ 0.25

VOH

High-level output voltage (5)

IOH = –4 mA, VV33DIO = 3 V

V33DIO

– 0.6

VIH

High-level input voltage

VV33DIO = 3 V

2.1

VIL

Low-level input voltage

VV33DIO = 3 V

1.1

IOH

Output sinking current

IOL

Output sourcing current

–4

SYSTEM PERFORMANCE

TWD

Watchdog time out range

Total time is: TWD ×

(WDCTRL.PERIOD + 1)

14.6

20.5

Time to disable DPWM output based on

active FAULT pin signal

High level on FAULT pin

Processor master clock (MCLK)

31.25

MHz

tDelay

Digital compensator delay(6)

(1 clock = 32 ns)

clocks

t(reset)

Pulse width needed at reset(1)

µs

Retention period of flash content (data

retention and program)

TJ = 25°C

100

years

Program time to erase one page or

block in data flash or program flash

Program time to write one word in data

flash or program flash

µs

f(PCLK)

Internal oscillator frequency

240

250

260

MHz

Sync-in or sync-out pulse width

SYNC pin

256

Flash read

MCLKs

Flash rrite

μs

ISHARE

Current share current source (See

Figure 7-16)

238

259

μA

RSHARE

Current share resistor (See Figure 7-

16)

9.75

10.3

kΩ

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