LXT381 — Octal E1 Line Interface Unit

4

Datasheet

Figures

1

LXT381 144-Pin Low-Profile Quad Flat Package (LQFP) Pin Assignments and

Package Markings5

2

LXT381 160-Pin Plastic Ball Grid Array (PBGA) Pin Assignments ....................... 6

3

Analog Loopback ................................................................................................ 15

4

Remote Looback ................................................................................................. 15

5

External Transmit/Receive Line Circuitry ........................................................... 17

6

LXT381 JTAG Architecture ................................................................................. 18

7

JTAG State Diagram ........................................................................................... 20

8

Analog Test Port Application .............................................................................. 26

9

Transmit Clock Timing ........................................................................................ 30

10

Receive Timing Diagram ..................................................................................... 31

11

JTAG Timing ....................................................................................................... 31

12

E1 Mask Templates ............................................................................................ 33

13

LXT381 144 Pin LQFP Package Dimensions ..................................................... 34

14

LXT381 160 Pin PBGA Package Dimensions..................................................... 35

Tables

1

LXT381 Pin Description ........................................................................................ 7

2

Operation Mode Summary .................................................................................. 16

3

TAP State Description ......................................................................................... 19

4

Boundary Scan Register (BSR) .......................................................................... 21

5

Device Identification Register (IDR) .................................................................... 24

6

Analog Port Scan Register (ASR) ....................................................................... 24

7

Instruction Register (IR) ...................................................................................... 26

8

Absolute Maximum Ratings ................................................................................ 27

9

Recommended Operating Conditions ................................................................. 27

11

Transmit Transmission Characteristics ............................................................... 28

10

DC Characteristics .............................................................................................. 28

12

Receive Transmission Characteristics ................................................................ 29

13

Analog Test Port Characteristics......................................................................... 30

14

Transmit Timing Characteristics.......................................................................... 30

15

Receive Timing Characteristics........................................................................... 30

16

JTAG Timing Characteristics .............................................................................. 31

17

Transformer Specifications ................................................................................. 32

18

G.703 2.048 Mbit/s Pulse Mask Specifications ................................................... 32