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LXT381II датащи(PDF) 30 Page - Intel Corporation

номер детали LXT381II
подробное описание детали  Octal E1 Line Interface Unit
PDF  36 Pages
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производитель  INTEL [Intel Corporation]
домашняя страница  http://www.intel.com
Logo INTEL - Intel Corporation

LXT381II датащи(HTML) 30 Page - Intel Corporation

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LXT381 — Octal E1 Line Interface
30
Datasheet
Table 13. Analog Test Port Characteristics
Parameter
Sym
Min.
Typ.
Max.
Unit
Test Condition
3 dB Bandwidth
at13db
-
5
-
MHz
Input voltage range
at1iv
0
-
VCC0
VCC1
V
Output voltage range
at2ov
0
-
VCC0
VCC1
V
Table 14. Transmit Timing Characteristics
Parameter
Sym
Min.
Typ.
Max.
Unit
Test Condition
Output pulse width
TW
219
244
269
ns
Transmit clock frequency
TCLK
-
2.048
-
MHz
Transmit clock tolerance
TCLKT
-50
-
+50
ppm
Transmit clock duty cycle
tDC
10
-
90
%
NRZ mode
TPOS/TNEG pulse width (RZ mode)
tMPW
236
-
252
ns
RZ mode (TCLK = H for
>16 clock cycles)
TPOS/TNEG to TCLK setup time
TSUT
20
-
-
ns
TCLK to TPOS/TNEG hold time
THT
20
-
-
ns
Delay time OE Low to driver Hi-Z
TOEZ
--
1
µS
Delay time TCLK Low to driver Hi-Z
TTZ
8-
15
µS
Figure 9. Transmit Clock Timing
Table 15. Receive Timing Characteristics
Parameter
Sym
Min.
Typ.
Max.
Unit
Test Condition
Rise/fall time 1
Tr
20
-
-
ns
@ CL=15 pF
RPOS/RNEG pulse width
Tpwl
200
244
300
ns
Receiver throughput delay
Trxd
-
85
-
ns
Delay time between RPOS/RNEG and RCLK
-
-
-
5
ns
1. For all digital outputs.
TCLK
TPOS
TNEG
tSUT
tHT



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