SI5341_16 datasheet(26/53 Pages) SILABS

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Table 5.7. Output Status Pin Specifications

(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, VDDS= 3.3V ± 5%, 1.8V ± 5%, TA= -40 to 85°C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Si5341/40 Status Output Pins (INTRb, SDA/SDIO)1

Output Voltage

VOH

IOH = -2 mA

VDDIO2 x

0.85

—

VOL

IOL = 2 mA

—

VDDIO2x

0.15

Si5341 Status Output Pins (LOLb)

Output Voltage

VOH

IOH = -2 mA

VDDIO2 x

0.85

—

VOL

IOL = 2 mA

—

VDDIO2 x

0.15

Si5340 Status Output Pins (LOLb, LOS_XAXBb)

Output Voltage

VOH

IOH = -2 mA

VDDS x 0.85

—

VOL

IOL = 2 mA

—

VDDSx 0.15

Notes:

1. The VOH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused

with I2C_SEL pulled high. VOL remains valid in all cases.

2. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Refer to the Family Reference Manual for more

details on register settings.

Table 5.8. Performance Characteristics

(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, TA= -40 to 85°C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

VCO Frequency Range

FVCO

13.5

—

14.4

GHz

PLL Loop Bandwidth

fBW

—

1.0

—

MHz

Initial Start-Up Time

tSTART

Time from power-up to

when the device gener-

ates clocks (Input Fre-

quency >48 MHz)

—

PLL Lock Time1

tACQ

fIN = 19.44 MHz

—

150

Output Delay Adjustment

tDELAY_frac

fVCO = 14 GHz

Delay is controlled by the

MultiSynth

—

0.28

—

tDELAY_int

—

71.4

—

tRANGE

—

±9.14

—

POR2 to Serial Interface Ready

tRDY

—

Si5341/40 Rev D Data Sheet

Electrical Specifications

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