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SI5341 датащи(PDF) 17 Page - Silicon Laboratories

номер детали SI5341
подробное описание детали  Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator
PDF  53 Pages
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производитель  SILABS [Silicon Laboratories]
домашняя страница  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SI5341 датащи(HTML) 17 Page - Silicon Laboratories

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4.2 High-Level Register Map
Table 4.1. High-Level Register Map
16-Bit Address
Content
8-bit Page Address
8-bit Register Address Range
00
00
Revision IDs
01
Set Page Address
02-0A
Device IDs
0B-15
Alarm Status
17-1B
INTR Masks
1C
Reset controls
2C-E1
Alarm Configuration
E2-E4
NVM Controls
FE
Device Ready Status
01
01
Set Page Address
08-3A
Output Driver Controls
41-42
Output Driver Disable Masks
FE
Device Ready Status
02
01
Set Page Address
02-05
XTAL Frequency Adjust
08-2F
Input Divider (P) Settings
30
Input Divider (P) Update Bits
35-3D
PLL Feedback Divider (M) Settings
3E
PLL Feedback Divider (M) Update Bit
47-6A
Output Divider (R) Settings
6B-72
User Scratch Pad Memory
FE
Device Ready Status
03
01
Set Page Address
02-37
MultiSynth Divider (N0-N4) Settings
0C
MultiSynth Divider (N0) Update Bit
17
MultiSynth Divider (N1) Update Bit
22
MultiSynth Divider (N2) Update Bit
2D
MultiSynth Divider (N3) Update Bit
38
MultiSynth Divider (N4) Update Bit
39-58
FINC/FDEC Settings N0-N4
59-62
Output Delay (Dt) Settings
63-94
Frequency Readback N0-N4
FE
Device Ready Status
Si5341/40 Rev D Data Sheet
Register Map
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0 | 16



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