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SI5341 датащи(PDF) 12 Page - Silicon Laboratories |
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SI5341 датащи(HTML) 12 Page - Silicon Laboratories |
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12 / 53 page ![]() 3.5.12 Zero Delay Mode A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs. The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally as shown in the figure below. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the outputs can be fed back to the FB_IN pins, although using the output driver that achieves the shortest trace length will help to minimize the input-to-output delay. It is recommended to connect OUT9 (Si5341) or OUT3 (Si5340) to FB_IN for external feedback. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feedback path connection is necessary for best performance. Zero Delay Mode Si5341 IN_SEL[1:0] IN0 IN0b IN1 IN1b IN2 IN2b ÷ P0 ÷ P1 ÷ P2 OUT0b VDDO0 OUT0 OUT2b VDDO2 OUT2 OUT3b VDDO3 OUT3 OUT7b VDDO7 OUT7 OUT8b VDDO8 OUT8 OUT9b VDDO9 OUT9 OUT1b VDDO1 OUT1 MultiSynth & Dividers FB_IN FB_INb External Feedback Path PD LPF ÷ Mn Md ÷ N9n N9d ÷R9 fFB =fIN fIN ÷Pfb PLL Figure 3.8. Si5341 Zero Delay Mode Setup 3.5.13 Sync Pin (Synchronizing R Dividers) All the output R dividers are reset to the default NVM register state after a power-up or a hard reset. This ensures consistent and re- peatable phase alignment across all output drivers to within ±100 ps of the expected value from the NVM download. Resetting the de- vice using the RSTb pin or asserting the hard reset bit will have the same result. The SYNCb pin provides another method of re-aligning the R dividers without resetting the device, however, the outputs will only align to within 50 ns when using the SYNCb pin. This pin is positive edge triggered. Asserting the sync register bit provides the same function as the SYNCb pin. A soft reset will align the outputs to within ±100 ps of the expected value based upon the Nx_DELAY parameter. 3.5.14 Output Crosspoint The output crosspoint allows any of the N dividers to connect to any of the clock outputs. Si5341/40 Rev D Data Sheet Functional Description silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 11 |
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