3.5.10 Synchronous/Asynchronous Output Disable Feature

Outputs can be configured to disable synchronously or asynchronously. The default state is synchronous output disable. In synchro-

nous disable mode the output will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt

pulses from occurring when disabling an output. In asynchronous disable mode the output clock will disable immediately without waiting

for the period to complete.

point switch. By default all clocks are phase aligned. A delay path (t0 - t4) associated with each of these dividers is available for applica-

tions that need a specific output skew configuration. Each delay path is controlled by a register parameter call Nx_DELAY with a resolu-

tion of ~0.28 ps over a range of ~±9.14 ns. This is useful for PCB trace length mismatch compensation. After the delay controls are

configured, the soft reset bit SOFT_RST must be set high so that the output delay takes effect and the outputs are re-aligned.

OUT2b

VDDO2

OUT2

VDDO3

OUT3b

OUT3

OUT1b

VDDO1

OUT1

OUT5b

VDDO5

OUT5

VDDO6

OUT6b

OUT6

OUT4b

VDDO4

OUT4

OUT7b

VDDO7

OUT7

VDDO8

OUT8b

OUT8

OUT0b

VDDO0

OUT0

VDDO9

OUT9b

OUT9

Figure 3.7. Example of Independently Configurable Path Delays

All delay values are restored to their NVM programmed values after power-up or after a hard reset. Delay default values can be written

to the NVM allowing a custom delay offset configuration at power-up or after a hardware reset.

Si5341/40 Rev D Data Sheet

Functional Description

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