LP8754 datasheet(11/53 Pages) TI1

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LP8754

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SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014

Protection Features Characteristics (continued)

Limits apply over the full ambient temperature range -40°C

≤ TA ≤ 85°C, VVDDA5V = VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V,

VOUT = 1.1 V, (unless otherwise noted).

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

THERMAL SHUTDOWN AND MONITORING

TSHUT

Thermal shutdown (TSD)

Threshold, Temperature rising

150

Hysteresis

TWARN

Thermal warning

Temperature rising, 1st warning, Interrupt

only

°C

Hysteresis

Thermal warning prior to TSD

Temperature rising, 2nd warning, Interrupt

120

and flag set

Hysteresis

6.9 I

2C Serial Bus Timing Parameters

Serial bus address is selected by the ADDR pin. Connect the pin to GND (addr = 60h), VIOSYS (addr = 61h), SDASYS (addr

= 62h), or SCLSYS (addr = 63h). Both of the serial buses share the same address; that is, if addr = 60h is selected for the

System bus, the Dynamic Voltage Scaling bus will respond to the same address. Start conditions are used to secure the I

slave address. During the I

2C bus start condition, it is detected whether the ADDR is connected to SDASYS, SCLSYS, GND,

or VIOSYS. The I

2C host should allow at least 500 µs before sending data to the LP8754 after the rising edge of the VIOSYS

line.

These specifications are ensured by design. Limits apply over the full ambient temperature range -40°C

≤ TA ≤ 85°C, VVDDA5V

= VVINBXX = 3.7 V, VVIOSYS = VNRST = 1.8 V, VOUT = 1.1 V, (unless otherwise noted).

SYMBOL

PARAMETER (See Figure 1)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL TIMING SPECIFICATIONS (SCL, SDA)(1)(2)(3)

Standard mode

100

kHz

Fast mode

400

kHz

fCLK

Serial clock frequency

High-speed mode, Cb = 100 pF (max)

3.4

MHz

High-speed mode, Cb = 400 pF (max)

(4)

1.7

MHz

Standard mode

4.7

µs

Fast mode

1.3

tLOW

SCL low time

High-speed mode, Cb = 100 pF (max)

160

High-speed mode, Cb = 400 pF (max)

(4)

320

Standard mode

4.0

µs

Fast mode

0.6

tHIGH

SCL high time

High-speed mode, Cb = 100 pF (max)

High-speed mode, Cb = 400 pF (max)

(4)

120

Standard mode

250

tSU;DAT

Data setup time

Fast mode

100

High-speed mode

Standard mode

3.45

µs

Fast mode

0.9

tHD;DAT

Data hold time

High-speed mode, Cb = 100 pF (max)

High-speed mode, Cb = 400 pF (max)

(4)

150

(1)

Unless otherwise stated, 'SDA' in this paragraph refers to both of the SDASR and SDASYS signals, and respectively 'SCL' refers to

SCLSR and SCLSYS signals.

(2)

Cb refers to the capacitance of one bus line. Cb is expressed in pF units. The specification table provided applies to both of the

interfaces; DVS and System interface.

(3)

The power-on default setting for the system bus and the DVS bus is High-speed-enabled, there is no handshaking required to initiate

High speed.

(4)

For bus line loads Cb between 100 pF and 400 pF the timing parameters must be linearly interpolated.

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