LP8754 datasheet(45/53 Pages) TI1

45 / 53 page

LP8754

www.ti.com

SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.5 V and 5 V. This input supply

should be well regulated and able to withstand maximum input current and maintain stable voltage without

voltage drop even at load transition condition. The resistance of the input supply rail should be low enough that

the input current transient does not cause too high drop in the LP8754 supply voltage that can cause false UVLO

fault triggering. If the input supply is located more than a few inches from the LP8754 additional bulk capacitance

may be required in addition to the ceramic bypass capacitors.

10 Layout

10.1 Layout Guidelines

The high frequency and large switching currents of the LP8754 make the choice of layout important. Good power

supply results will only occur when care is given to proper design and layout. Bad layout will affect noise pickup

and generation and can cause a good design to perform with less-than-expected results. With a range of output

currents from milliamps to 10 A, good power-supply layout is more challenging than for most general PCB

design. The following steps should be used as a reference to ensure the device is stable and maintains proper

voltage and current regulation across its intended operating voltage and current range:

1. Place CIN as close as possible to the VINBXX pin and the GND pin. Route the VIN trace wide and thick to

avoid IR drops. The trace between the input capacitor's positive node and LP8754’s VINBXX pin(s) as well

as the trace between the input capacitor's negative node and power GND pin(s) must be kept as short as

possible. The input capacitance provides a low-impedance voltage source for the switching converter. The

parasitic inductance on these traces must be kept as tiny as possible for proper device operation.

2. The output filter for each buck, consisting of COUT and L, converts the switching signal at SW to the noiseless

output voltage. For optimal EMI behavior, it should be placed as close as possible to the device, keeping the

switch node small. Route the traces between the LP8754's output capacitors and the load's input capacitors

direct and wide to avoid losses due to the IR drop.

3. Input for analog blocks (VDDA5V and GNDA) should be isolated from noisy signals. Connect VDDA5V

directly to a quiet system voltage node and GNDA to a quiet ground point where no IR drop occurs. For

additional noise immunity, adding a high-frequency decoupling capacitor of 100 nF to 1 µF is recommended.

Place the decoupling capacitor as close to the VDDA5V pin as possible. VDDA5V trace is low current, so the

trace width does not need to be optimized.

4. If the processor load supports voltage remote sensing, connect the LP8754’s feedback pins FBBXX to the

respective sense pins on the processor. The sense lines are susceptible to noise. They must be kept away

from noisy signals such as GNDBXX, VIN, and SW, as well as high bandwidth signals such as the I

2C. Avoid

both capacitive as well as inductive coupling by keeping the sense lines short, direct, and close to each

other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible.

Running the signal as a differential pair is recommended.

5. GNDBXX, VIN, and SW should be routed on thick layers. They must not surround inner signal layers which

are not able to withstand interference from noisy GNDBXX, VIN, and SW. This can create noise coupling to

inner signal layers.

Due to the small package of this converter and the overall small solution size, the thermal performance of the

PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and

convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of

a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures.

Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB

designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board

(RθJB) thermal resistances, thereby reducing the device junction temperature, TJ. It's strongly recommended to

perform a careful system-level 2D or full 3D dynamic thermal analysis at the beginning of the product design

process, using a thermal modeling analysis software.

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