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LP8754 датащи(PDF) 32 Page - Texas Instruments |
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LP8754 датащи(HTML) 32 Page - Texas Instruments |
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32 / 53 page ![]() LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com 7.6.11 FLAGS_1 Address: 0x0E D7 D6 D5 D4 D3 D2 D1 D0 Reserved I_LOAD_READ UVLO T_WARNING THSD OVP SCP Y Bits Field Type Default Description 7:6 Reserved R/W 00 5 I_LOAD_READY R/W 0 Flag Bit(1) 1 = Buck load current measurement data ready 0 = Buck load current measurement data not ready 4 UVLO R/W 0 Flag Bit (1) 1= Input undervoltage lockout (UVLO): Input voltage sagged below UVLO threshold. 0 = No UVLO 3 T_WARNING R/W 0 Flag Bit (1) 1= Thermal warning: The IC temperature exceeds 120°C, in advance of the thermal shutdown protection. 0 = No thermal warning 2 THSD R/W 0 Flag Bit (1) 1 = Thermal shutdown event detected 0 = No thermal shutdown 1 OVP R/W 0 Flag Bit (1) 1= Indicates overvoltage protection (OVP) circuit activation. 0 = No OVP event. The OVP circuitry monitors VDDA5V power input. 0 SCP R/W 0 Flag Bit (1) 1= Indicates short-circuit protection (SCP) circuit activation. The bit is activated when a short-circuit condition is detectedon output rail. 0 = No SCP event (1) The flag bit(s) can be cleared only by writing a zero to the associated register bit(s) or power cycling the device (VVIOSYS to LOW). Reading or RESET does not clear the flag bits. After clearing, the OVP, SCP fault flag(s) will be raised again '1' if the fault condition persists. The THSD flag will remain '0' after clear, even though the fault condition persists. Any unmasked flag bit High will cause the interrupt to be asserted on the INT pin. The INT pin will be pulled Low until all the unmasked flags are clear again. 7.6.12 INT_MASK_0 Address: 0x0F D7 D6 D5 D4 D3 D2 D1 D0 Reserved MASK_nPG_B MASK_OVP MASK_SCP 0 Bits Field Type Default Description 7:3 Reserved R/W 1 1111 2 MASK_nPG_B0 R/W 0 Interrupt mask for power good fault flag 1 = nPG_B0 does not set interrupt. 0 = nPG_B0 sets interrupt, when triggered. 1 MASK_OVP R/W 0 Interrupt mask for Overvoltage Protection (OVP) fault flag 1 = OVP does not set interrupt. 0 = OVP sets interrupt, when triggered. 0 MASK_SCP R/W 0 Interrupt mask for short-circuit protection SCP fault flag 1 = SCP does not set interrupt. 0 = SCP sets interrupt, when triggered. 7.6.13 GENERAL Address: 0x10 32 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 |
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