CLC5902 datasheet(19/28 Pages) NSC

19 / 28 page

Rev. 3.05 May 27, 1999

mitted first. When this mode is selected, the I/Q samples

are packed regardless of the state of MUX_MODE, and

the data is sent as mI/eI/eQ/mQ which allows the two

exponents to form an 8-bit word. This is shown in Figure

29(d). For all formats, once the defined length of the word

is complete, SCK stops toggling.

Parallel Outputs

Output data from the channels can also be taken from a

16-b it par allel po rt. A 3-bit w ord a pplie d to the

POUT_SEL[2:0] pins determines which 16-bit segment is

multiplexed to the parallel port. Table 3 defines this map-

ping. To allow for bussing of multiple chips, the parallel

port is tri-stated unless POUT_EN is low. The RDY sig-

nal indicates the start of an OSP and that new data is ready

at the parallel output. The user has one OSP to cycle

through whichever registers are needed. The RATE regis-

ter must be set so that each OSP is at least 5 SCK periods.

Parallel Port Output Numeric Formats

The I/Q samples can be rounded to 16 or 24 bits or the full

32 bit word can be read. By setting the word size to 32 bits

it is possible to read out the top 16 bits and only observe

the top 8 bits if desired. Additionally, the output samples

can be formatted as floating point numbers with an 8-bit

mantissa and a 4 bit exponent. For the fixed-point formats,

the valid bits are justified into the MSBs of the registers of

Table 3 and all other bits are set to zero. For the floating

point format, the valid bits are placed in the upper 16 bits

of the appropriate channel register using the format 0000/

eI/mI for the I samples.

SCK

SFS

AOUT

I15

I14

Q15

Q14

(a) UNPACKED MODE, FRAME SYNC AT THE START OF EACH WORD

SCK

SFS

AOUT

I15

I14

Q15

Q14

(b) PACKED MODE, ONE FRAME SYNC AT THE START OF EACH DOUBLE-WORD TRANSFER

clock stops and data is zero after transfers are complete

RDY

SFS

AOUT

MUX_MODE=0

MUX_MODE=1

Output Sample Period (OSP)

SFS

SCK

SFS

AOUT

mI7

eI3

eI0

eQ3

(d) FLOATING POINT FORMAT

eQ0

mQ0

mI0

mQ7

leading edge of RDY aligns with leading edge of SFS

Figure 29

Serial output formats. Refer to Figure 9 for detailed timing information

RDY is 4 CK periods wide

mI6

eI2

clock stops and data is zero after transfers are complete

POUT_SEL

Normal Register

Contents

Floating Point

IA upper 16 bits

0000/eIA/mIA

IA lower 16 bits

0x0000

QA upper 16 bits

0000/eQA/mQA

QA lower 16 bits

0x0000

IB upper 16 bits

0000/eIB/mIB

IB lower 16 bits

0x0000

QB upper 16 bits

0000/eQB/mQB

QB lower 16 bits

0x0000

Table 3

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