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CLC5902 датащи(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали CLC5902
подробное описание детали  Dual Digital Tuner/AGC
PDF  28 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
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CLC5902 датащи(HTML) 4 Page - National Semiconductor (TI)

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Rev. 3.05 May 27, 1999
4
©1999 National Semiconductor Corporation
A. tSFSV refers to the rising edge of SCK when SCK_POL=0 and the
falling edge when SCK_POL=1.
B. tOV refers to the rising edge of SCK when SCK_POL=0 and the fall-
ing edge when SCK_POL=1.
C. tRDYV refers to the rising edge of RDY when RDY_POL=0 and the
falling edge when RDY_POL=1.
1. These parameters are 100% tested at 25°C.
2. Typical specifications are the mean values of the distributions of deliv-
erable CLC5902s tested to date.
3. Min/max ratings are based on product characterization and simulation.
Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
NOTE: Absolute maximum ratings are limiting values, to be applied
individually, and beyond which the serviceability of the circuit may be
impaired. Functional operability under any of these conditions is not nec-
essarily implied. Exposure to maximum ratings for extended periods may
affect device reliability.
Enable Time TCK to Data Out (Figure 13)
tPZH
035
ns
1
Setup Time Data to TCK (Figure 13)
tS
10
ns
1
Setup Time TDI to TCK (Figure 13)
tS
10
ns
1
Setup Time TMS to TCK (Figure 13)
tS
15
ns
1
Hold Time Data to TCK (Figure 13)
tH
55
ns
1
Hold Time TCK to TDI (Figure 13)
tH
55
ns
1
Hold Time TCK to TMS (Figure 13)
tH
10
ns
1
TCK Pulse Width High (Figure 13)
tWH
55
ns
1
TCK Pulse Width Low (Figure 13)
tWL
40
ns
1
TCK Maximum Frequency (Figure 13)
JTAGFMAX
10
MHz
1
Control Setup before the controlling signal goes low (Figure 14)
tCSU
5ns
1
Control hold after the controlling signal goes high (Figure 14)
tCHD
5ns
1
Controlling strobe pulse width (Write) (Figure 14)
tCSPW
30
ns
1
Control output delay controlling signal low to D (Read) (Figure 14)
tCDLY
30
ns
1
Control tri-state delay after controlling signal goes high (Figure 14)
tCZ
20
ns
1
Dynamic Supply Current (FCK =52MHz, N=48)
ICC
230
280
mA
1
Dynamic Supply Current (FCK =52MHz, N=8)
ICC
260
320
mA
1
PARAMETER (CL=50pF)
SYMBOL
MIN
TYP
MAX
UNITS
Notes
Positive Supply Voltage (VCC)
-0.3V to 4.2V
Voltage on Any Input or Output Pin
-0.3V to VCC+0.5V
Input Current at Any Pin
±25mA
Package Input Current
±50mA
Package Dissipation at TA=25°C
1W
ESD Susceptibility
Human Body Model
Machine Model
1500V
100V
Soldering Temperature, Infrared, 10 seconds
300°C
Storage Temperature
-65°C to 150°C
Notes A - C
Notes 1 - 3
Absolute Maximum Ratings
Positive Supply Voltage (VCC)
3.3V ±10%
Operating Temperature Range
-40°C to +85°C
Package
θja
θjc
128 pin PQFP
39°C/W
TBD°C/W
Transistor Count
1.2 million
Order Code
Temperature
Range
Description
CLC5902VLA
-40°C to
+85°C
128-pin PQFP (industrial
temperature range)
CLC-DRCS-PCASM
Fully loaded Diversity
Receiver Chipset evaluation
board and control panel soft-
ware.
CLC-CAPT-PCASM
Data Capture board for the
DRCS with Matlab analysis
routines.
Recommended Operating Conditions
Package Thermal Resistance
Reliability Information
Ordering Information



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