CLC5902 datasheet(14/28 Pages) NSC

14 / 28 page

Rev. 3.05 May 27, 1999

Oscillator (NCO) circuit to generate sine and cosine sig-

nals used by the digital mixer. The NCOs can be synchro-

nized with NCOs on other chips via the sync pin SI. This

allows multiple down converter outputs to be coherently

combined, each with a unique phase and amplitude.

The tuning frequency is set by loading the FREQ register

according to the formula FREQ = 232F/FCK, where F is

the desired tuning frequency and FCK is the chip’s clock

rate. FREQ is a 2’s complement word. The range for F is

from -FCK/2 to +FCK(1-2

-31)/2.

In some cases the sampling process causes the order of the

I and Q components to be reversed. Should this occur sim-

ply invert the polarity of the tuning frequency F.

The 2’s complement format represents full-scale negative

as 10000000 and full-scale positive as 01111111 for an 8-

bit example.

The 16 bit phase offset is set by loading the PHASE regis-

ter according to the formula PHASE = 216P/2

π, where P

is the desired phase in radians ranging between 0 and 2

π.

PHASE is an unsigned 16-bit number. P ranges from 0 to

π(1-2-16).

Phase dithering can be enabled to reduce the spurious sig-

nals created by the NCO due to phase truncation. This

truncation is unavoidable since the frequency resolution is

much finer than the phase resolution. With dither enabled,

spurs due to phase truncation are below -100 dBc for all

frequencies and phase offsets. Each NCO has its own

dither source and the initial state of one is maximally off-

set with respect to the other so that they are effectively

uncorrelated. The phase dither sources are on by default.

They are independently controlled by the DITH_A and

DITH_B bits. The amplitude resolution of the ROM cre-

ates a worst-case spur amplitude of -101dBc rendering

amplitude dither unnecessary.

The spectrum plots in Figure 16 show the effectiveness of

phase dither in reducing NCO spurs due to phase trunca-

tion for a worst-case example (just below FS/8). With

dither off, the spur is at -86.4dBFS. With dither on, the

spur is below -125dBFS, disappearing into the noise floor.

This spur is spread into the noise floor which results in an

SNR of -83.6dBFS.

Figure 17 shows the spur levels as the tuning frequency is

scanned over a narrow portion of the frequency range. The

spurs are again a result of phase quantization but their

locations move about as the frequency scan progresses. As

before, the peak spur level drops when dithering is

enabled. When dither is enabled and the fundamental fre-

quency is exactly at FS/8, the worst-case spur due to

amplitude quantization can be observed at -101dBc in Fig-

ure 18.

Four Stage CIC Filter

The mixer outputs are decimated by a factor of N in a four

stage CIC filter. N is programmable to any integer

between 8 and 2048. Decimation is programmed in the

DEC register where DEC = N - 1. The programmable dec-

imation allows the chip’s usable output bandwidth to range

from about 2.6kHz to 1.3MHz when the input data rate

(which is equal to the chip’s clock rate, FCK) is 52 MHz. A

block diagram of the CIC filter is shown in Figure 19.

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-160

-140

-120

-100

-80

-60

-40

-20

Frequency Normalized to FS

Figure 17

NCO Spurs due to Phase Quantization

Complex NCO Output

Phase Dither Disabled

NCO frequency swept through FS/8

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-160

-140

-120

-100

-80

-60

-40

-20

Frequency Normalized to FS

Figure 18

Worst Case Amplitude Spur, NCO at FS/8

Complex NCO Output

Phase Dither Enabled

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