©1999 National Semiconductor Corporation

7

Rev. 3.05 May 27, 1999

Pin Descriptions

Signal

Pin

DESCRIPTION

MR

45

MASTER RESET, Active low

Resets all registers within the chip. ASTROBE and BSTROBE are asserted during MR.

AIN[13:0],

BIN[13:0]

4:10,12:18

22:28,30:36

INPUT DATA, Active high

2’s complement input data. AIN[13] and BIN[13] are the MSBs. The data is clocked into the chip on the

rising edge of the clock (CK). The CLC595X connects directly to these input pins with no additional logic.

AOUT

BOUT

(12mA drive)

82

78

SERIAL OUTPUT DATA, Active high

The 2’s complement serial output data is transmitted on these pins, MSB first. The output bits change on

the rising edge of SCK (falling edge if SCK_POL=1) and should be captured on the falling edge of SCK

(rising if SCK_POL=1). These pins are tri-stated at power up and are enabled by the SOUT_EN control

register bit. See Figure 9 and Figure 29 timing diagrams. In Debug Mode AOUT=DEBUG[1],

BOUT=DEBUG[0].

AGAIN[2:0],

BGAIN[2:0]

125:127

40:42

OUTPUT DATA TO DVGA, Active high

3 bit bus that sets the gain of the DVGA determined by the AGC circuit.

ASTROBE,

BSTROBE

124

43

DVGA STROBE, Active low

Strobes the data into the DVGA. See Figure 8 and Figure 33 timing diagrams.

SCK

(12mA drive)

80

SERIAL DATA CLOCK, Active high or low

The serial data is clocked out of the chip by this clock. The active edge of the clock is user programmable.

This pin is tri-stated at power up and is enabled by the SOUT_EN control register bit. See Figure 9 and Fig-

ure 29 timing diagrams. In Debug Mode outputs an appropriate clock for the debug data.

SFS

(12mA drive)

81

SERIAL FRAME STROBE, Active high or low

The serial word strobe. This strobe delineates the words within the serial output streams. This strobe is a

pulse at the beginning of each serial word (PACKED=0) or each serial word I/Q pair (PACKED=1). The

polarity of this signal is user programmable. This pin is tri-stated at power up and is enabled by the

SOUT_EN control register bit. See Figure 9 and Figure 29 timing diagrams. In Debug Mode

SFS=DEBUG[2].

POUT[15:0]

(12mA drive)

84,86:88,90,91,

93:97,104:106,

108,109

PARALLEL OUTPUT DATA, Active high

The output data is transmitted on these pins in parallel format. The POUT_SEL[2..0] pins select one of

eight 16-bit output words. The POUT_EN pin enables these outputs. POUT[15] is the MSB. In Debug

Mode POUT[15..0]=DEBUG[19..4].

POUT_SEL[2:0]

112:114

PARALLEL OUTPUT DATA SELECT, Active high

The 16-bit output word is selected with these 3 pins according to Table 3. Not used in Debug Mode.

POUT_EN

111

PARALLEL OUTPUT ENABLE. Active low

This pin enables the chip to output the selected output word on the POUT[15:0] pins. Not used in Debug

Mode.

RDY

(12mA drive)

77

READY FLAG, Active high or low

The chip asserts this signal to identify the beginning of an output sample period (OSP). The polarity of this

signal is user programmable. This signal is typically used as an interrupt to a DSP chip, but can also be used

as a start pulse to dedicated circuitry. This pin is active regardless of the state of SOUT_EN. In Debug

Mode RDY=DEBUG[3].

CK

20

INPUT CLOCK. Active high

The clock input to the chip. The AIN, BIN, and SI input signals are clocked into the chip on the rising edge

of this clock.

SI

46

SYNC IN. Active low

The sync input to the chip. The decimation counters, dither, and NCO phase can be synchronized by SI.

This sync is clocked into the chip on the rising edge of the input clock (CK). Tie this pin high if external

sync is not required. All sample data is flushed by SI. To properly initialize the DVGA ASTROBE and

BSTROBE are asserted during SI.

D[7:0]

(12mA drive)

62,63,69:73,75

DATA BUS. Active high

This is the 8 bit control data I/O bus. Control register data is loaded into the chip or read from the chip

through these pins. The chip will only drive output data on these pins when CE is low, RD is low, and WR

is high.

Table 1

CLC5902 Pin Descriptions