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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CLC5902 датащи(PDF) 3 Page - National Semiconductor (TI) |
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CLC5902 датащи(HTML) 3 Page - National Semiconductor (TI) |
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3 / 28 page  ©1999 National Semiconductor Corporation 3 Rev. 3.05 May 27, 1999 DC Characteristics AC Characteristics CLC5902 Electrical Characteristics (VCC=+3.3V, 52MHz, CIC Decimation=48, F2 Decimation=2, Tmin=-40°C, Tmax=+85°C; unless specified) PARAMETER SYMBOL MIN TYP MAX UNITS Notes Voltage input low VIL -0.5 0.8 V 1 Voltage input high VIH 2.0 VCC+0.5 V 1 Input current IIN 10 uA 1 Voltage output low (IOL = 4mA/12mA, see pin description) VOL 0.4 V 1 Voltage output high (IOH = -4mA/-12mA, see pin description) VOH 2.4 V 1 Input capacitance CIN 4.0 pF 3 PARAMETER (CL=50pF) SYMBOL MIN TYP MAX UNITS Notes Clock (CK) Frequency (Figure 7) FCK 52 MHz 1 Spurious Free Dynamic Range SFDR -100 dBFS Signal to Noise Ratio SNR -127 dBFS Tuning Resolution 0.02 Hz Phase Resolution 0.005 ° MR Active Time (Figure 5) tMRA 4 CK periods 1 MR Inactive to first Control Port Access (Figure 5) tMRIC 10 CK periods 1 MR Setup Time to CK (Figure 5) tMRSU 9ns 1 MR Hold Time to CK (Figure 5) tMRH 2ns 1 MR Inactive to A|BSTROBE Release (Figure 5) tMRSR 17 ns SI Setup Time to CK (Figure 6) tSISU 9ns 1 SI Hold Time from CK (Figure 6) tSIH 2ns 1 SI Pulse Width (Figure 6) tSIW 4 CK periods 1 SI Inactive to A|BSTROBE Release (Figure 6) tSISR 17 ns CK duty cycle (Figure 7) tCKDC 40 60 % 1 CK rise and fall times (VIL to VIH) (Figure 7) tRF 3ns 1 Input setup before CK goes high (A|BIN) (Figure 7) tSU 7ns 1 Input hold time after CK goes high (Figure 7) tHD 3ns 1 A|BSTROBE Pulse Width (Figure 8) tSTBPW 1 CK period 2 A|BGAIN Valid Setup before A|BSTROBE (Figure 8) tGSU 1 CK period 2 AGC_EN Active Width (Figure 8) tENW 2 CK periods 1 SCK to SFS Valid (Table Note A) (Figure 9) tSFSV 07 ns 1 SCK to A|BOUT Valid (Table Note B) (Figure 9) tOV 07 ns 1 RDY Pulse Width (Figure 9) tRDYW 4 CK periods 1 POUT_EN Active to POUT[15..0] Valid (Figure 10) tOENV 15 ns 1 POUT_EN Inactive to POUT[15..0] Tri-State (Figure 10) tOENT 15 ns 1 PSEL[2..0] to POUT[15..0] Valid (Figure 11) tSELV 20 ns 1 RDY to POUT[15..0] New Value Valid (Table Note C) (Figure 12) tRDYV 10 ns 1 Propagation Delay TCK to TDO (Figure 13) tPLH 30 ns 1 Propagation Delay TCK to Data Out (Figure 13) tPHL 35 ns 1 Disable Time TCK to TDO (Figure 13) tPLZ 35 ns 1 Disable Time TCK to Data Out (Figure 13) tPHZ 35 ns 1 Enable Time TCK to TDO (Figure 13) tPZL 035 ns 1 |
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