THS1041

SLAS289C − OCTOBER 2001 − REVISED OCTOBER 2004

8

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PARAMETER MEASUREMENT INFORMATION

See Note A

WE

OE

I/O

Input

ADC Output

ADC Output

Hi-Z

Hi-Z

tw(WP)

td(OEW)

td(WOE)

td(DEN)

tsu

th

td(DZ)

NOTE A: All timing measurements are based on 50% of edge transition.

See Note B

NOTE B: Output data is converted ADC digital data. The input data is stored in the internal write only control registers.

Figure 1. Write Timing Diagram

See

Note A

NOTE A: All timing measurements are based on 50% of edge transition.

Analog

Input

Input Clock

Digital

Output

Sample 1

Sample 2

Sample 3

Sample 4

Sample 5

tc

tw(CKH)

tw(CKL)

td(o)

(I/O Pad Delay or

Propagation Delay)

Pipeline Latency

Sample 1

Sample 2

Sample 6

OE

td(DEN)

td(DZ)

Sample 7

Figure 2. Digital Output Timing Diagram