THS1041CPWR datasheet(31/42 Pages) TI1

31 / 42 page

THS1041

SLAS289C − OCTOBER 2001 − REVISED OCTOBER 2004

www.ti.com

APPLICATION INFORMATION

initial clamp acquisition time (continued)

Initial acquisition can be performed in two ways:

D Pulsing the CLAMP pin as in normal operation. Provided that clamp droop (see below) is negligible, initial

acquisition is complete when the total clamped (CLAMP = high) time equals TACQ.

D Pulling the CLAMP pin high for the required acquisition time before starting normal operation. This method

is faster, though possibly less convenient for the user to implement.

clamp droop

The charging currents drawn by the sample-and-hold switched capacitor input can charge or discharge CIN,

causing the dc voltage at AIN+ to drift towards the dc bias voltage at AIN− during the time between clamp pulses.

This effect is called clamp droop.

Voltage droop is a function of the AIN+ and AIN− input currents to the THS1041, IIN, and the time between clamp

intervals, tD:

DROOP [

(approximate)

Worst case droop between clamping intervals occurs for maximum input bias current. Maximum input current

is IINFS, which occurs when the input level is at its maximum or minimum.

For example, at 40 MSPS IINFS is approximately 20 µA for a 2-V input range at AIN (assuming 2 V appear across

RIN2—see driving the sample and hold reference inputs to calculate RIN2). Note that IINFS may vary from this

±30% because of processing variations and voltage dependencies. Designs should allow for this variation.

If the time td between clamping intervals is 63.5 µs and CIN is 1 µF, then the maximum clamp level droop between

clamp pulses is

DROOP

(max)

+ 20 mA 1 mF

63.5

ms + 1.25 mV (approximate, ignoring 30% tolerance)

+ 0.62 LSB at PGA gain + 1, 2 V ADC references

If this droop is greater than can be tolerated in the application, then increase CIN to slow the droop and hence

reduce the voltage change between clamp pulses.

If a high leakage capacitor is used for coupling the input source to the AIN pin then the droop may be significantly

worse than calculated above. Avoid using electrolytic and tantalum coupling capacitors as these have higher

leakage currents than nonpolarized capacitor types. Electrolytic and tantalum capacitors also tend to have

higher parasitic inductance, which can cause problems at high input frequencies.

steady-state clamp voltage error

During the clamp pulse (CLAMP = high), the dc voltage on AIN is refreshed from the clamp voltage. Provided

that droop is not excessive, clamping fully reverses the effect of droop. However, using very short clamp pulses

with long intervals between pulses (td) can result in a steady-state voltage difference, VCOS, between the dc

voltage at AIN and V(Clamp).

Figure 47 shows the approximate voltage waveform at AIN resulting from a a large clamp droop during td and

clamp voltage reacquisition during the clamp pulse time, tc.

(17)

(18)

THS1041CPWR датащи(PDF) 31 Page - Texas Instruments

THS1041CPWR датащи(HTML) 31 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

датащи скачать

ссылки URL