TUSB5052 datasheet(64/82 Pages) TI

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9−2

9.1.3

IEPINT: Input Endpoint Interrupt Request Register

R/O

BIT

NAME

RESET

FUNCTION

7−0

E[7:0]

These bits indicate which input endpoint interrupt is pending (IEP 7−0)

E[n] = 0

No interrupt pending (n = 7:0).

E[n] = 1

Indicates that the corresponding endpoint generated an interrupt. This is set by the hardware and is

cleared when the MCU writes to the VECINT register.

9.1.4

OEPINT: Output Endpoint Interrupt Request Register

R/O

BIT

NAME

RESET

FUNCTION

7−0

E[7:0]

These bits indicate which input endpoint interrupt is pending (OEP 7−0).

E[n] = 0

No interrupt pending

E[n] = 1

Indicates that the corresponding endpoint generated an interrupt. This is set by the hardware and is

cleared when the MCU writes to the VECINT register.

9.1.5

VECINT: Vector Interrupt Register

This register contains a vector value, which identifies the internal interrupt source that trapped to location 0003H.

Writing (any value) to this register removes the vector and updates the next vector value (if another interrupt is

pending). Note that the vector value is offset; therefore, its value is in increments of two (bit-0 is set to 0). When no

interrupt is pending, the vector is set to 00h (see Table 9−2). As shown, the interrupt vector is divided to two fields:

I[2:0] and G[3:0]. The I-field defines the interrupt source within a group (on a first-come-first-served basis). In the

G-field, which defines the group number, group G0 is the lowest, and G15 is the highest, priority.

R/O

BIT

NAME

RESET

FUNCTION

RSV

Reserved

3−1

I[2:0]

000b

This field defines the interrupt source in a given group (see Table 9−2). Bit-0 = 0 always; therefore, vector values

are offset by two.

7−4

G[3:0]

0x0

This field defines the interrupt group. I[2:0] and G[3:0] combine to produce the actual interrupt vector.

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