TUSB5052 datasheet(44/82 Pages) TI

44 / 82 page

6−2

6.1.1

DMACDR[2:1]: DMA Channel Definition Register (2 UART Transmit Channels)

These registers are used to define the EDB number that the DMA uses for data transfer to the UARTs. In addition,

these registers define the data transfer direction and select X or Y as the transaction buffer.

5432

INE

CNT

XY_WR_PROT

R/W

BIT

NAME

RESET

FUNCTION

2−0

E[2:0]

Endpoint descriptor pointer. This field points to a set of EDB registers that is to be used for a given transfer.

XY_WR_PROT

XY protection bit. This bit always returns 1 when read. If this bit is 1 during a write, XY (bit 4) is not affected. If

this bit is 0 during a write, the value of XY is loaded from MCU bit 4.

X/Y buffer select bit. Valid only when CNT = 0

XY = 0 Next buffer to transmit/receive is the X buffer

XY = 1 Next buffer to transmit/receive is the Y buffer

CNT

DMA continuous transfer control bit. This bit defines the mode of the DMA transfer.

CNT

CNT = 0

Burst Mode: DMA stops the transfer when the byte count is zero or when a partial packet has

been received (byte count < 64). At the end of transfer, the high-to-low transition of EN interrupts

the MCU (if enabled). In this mode, the X/Y bit is set by the MCU to define the current buffer (X or

Y). Single buffering is required in this mode.

CNT = 1

Continuous Mode: In this mode, the DMA and UBM alternate between the X and Y buffers. The

DMA sets the X/Y bit and the UBM uses it for the transfer. The DMA alternates between the X/Y

buffers and continues transmitting (from X/Y buffer) without MCU intervention. The DMA

terminates, and interrupts the MCU, under the following conditions:

1. When the UBM byte count < buffer size (in EDB), the DMA transfers the partial packet and

interrupts the MCU on completion.

2. Transaction timer expires. The DMA interrupts the MCU.

INE

DMA interrupt enable/disable bit. This bit is used to enable/disable the interrupt on transfer completion.

INE

INE = 0

Interrupt is disabled. In addition, PPKT and TXFT do not clear the EN bit and the DMAC is not

disabled.

INE = 1

Enables the EN interrupt. When this bit is set, the DMA interrupts the MCU on a 1-to-0 transition

of the EN bit. (When transfer is completed, EN = 0)

DMA channel enable bit. The MCU sets this bit to start the DMA transfer. When the transfer completes, or

when it is terminated due to error, this bit is cleared. The 1 to 0 transition of this bit generates an interrupt (if

interrupt is enabled).

EN = 0

DMA is halted. The DMA is halted when the byte count reaches zero or when transaction

time-out occurs. When halted, the DMA updates the byte count, sets NAK = 0 in OEDB, and

interrupts the MCU (if INE = 1).

EN = 1

Setting this bit starts the DMA transfer.

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