AD9956

Rev. 0 | Page 12 of 32

Table 3. 48-Lead LFCSP Pin Function Description

Pin No.

Mnemonic

Description

1, 3, 8, 26, 30,

34, 37, 43, 49

AGND

Analog Ground.

2, 4, 7, 27, 31,

38, 44, 48

AVDD

Analog Core Supply (1.8 V).

5

IOUT

DAC Analog Output.

6

IOUT

DAC Analog Complementary Output.

9

I/O_RESET

Resets the serial port when synchronization is lost in communications but does not reset the de-

vice itself (ACTIVE HIGH). When not being used, this pin should be forced low, because it floats to

the threshold value.

10

RESET

Master RESET. Clears all accumulators and returns all registers to their default values (ACTIVE

HIGH).

11, 25

DVDD

Digital Core Supply (1.8 V).

12, 24

DGND

Digital Ground.

13

SDO

Serial Data Output. Used only when device is programmed for 3-wire serial data mode.

14

SDI/O

Serial Data I/O. When the part is programmed for 3-wire serial data mode, this is input only; in

2-wire mode, it serves as both the input and output.

15

SCLK

Serial Data Clock. Provides the clock signal for the serial data port.

16

CS

Active Low Signal That Enables Shared Serial Busses. When brought high, the serial port ignores

the serial data clocks.

17

DVDD_I/O

Digital Interface Supply (3.3 V).

18

SYNC_OUT

Synchronization Clock Output.

19

PLL_LOCK/SYNC_IN

Bidirectional Dual Function Pin. Depending on device programming, it is either the DDS’ synchro-

nization input (allows alignment of multiple subclocks) or the PLL lock detect output signal.

20

I/O_UPDATE

This input pin, when set high, transfers the data from the I/O buffers to the internal registers on the

rising edge of the internal SYNC_CLK, which can be observed on SYNC_OUT.

21 to 23

PS0 to PS2

Profile Select Pins. Specify one of eight frequency tuning word/phase offset word profiles. In linear

sweep mode, PS0 determines the state of the sweep. In linear sweep no dwell mode, PS0 is a trig-

ger that initiates the sweep. PS1 and PS2 have no function during linear sweep mode or linear

sweep no dwell mode.

28

REFCLK

RF Divider and DDS REFCLK Complementary Input.

29

REFCLK

RF Divider and DDS REFCLK Input.

32

DRV

CML Driver Complementary Output.

33

DRV

CML Driver Output.

35

CP_VDD

Charge Pump Supply Pin (3.3 V). To minimize noise on the charge pump, isolate this supply from

DVDD_I/O.

36

CP_OUT

Charge Pump Output.

39

PLLREF

Phase Frequency Detector Reference Input.

40

PLLREF

Phase Frequency Detector Reference Complementary Input.

41

PLLOSC

Phase Frequency Detector Oscillator (Feedback) Complementary Input.

42

PLLOSC

Phase Frequency Detector Oscillator (Feedback) Input.

45

CP_RSET

Charge Pump Current Set (Program Charge Pump Current with a Resistor to AGND).

46

DRV_RSET

CML Driver Output Current Set (Program CML Output Current with a Resistor to AGND).

47

DAC_RSET

DAC Output Current Set (Program DAC Output Current with a Resistor to AGND).

Note that the exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. In order for the

device to function properly, the paddle MUST be attached to analog ground.