STM32F446RC datasheet(171/201 Pages) STMICROELECTRONICS

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DocID027107 Rev 5

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STM32F446xC/E

Electrical characteristics

174

6.3.27

Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 104 for DCMI are derived

from tests performed under the ambient temperature, fHCLK frequency and VDD supply

voltage summarized in Table 16, with the following configuration:

•

DCMI_PIXCLK polarity: falling

•

DCMI_VSYNC and DCMI_HSYNC polarity: high

•

Data formats: 14 bits

Table 103. LPSDR SDRAM write timings(1)(2)

1. CL = 10 pF.

2. Guaranteed based on test during characterization.

Symbol

Parameter

Min

Max

Unit

F(SDCLK)

Frequency of operation

MHz

tw(SDCLK)

FMC_SDCLK period

2THCLK - 0.5

2THCLK + 0.5

td(SDCLKL _Data)

Data output valid time

th(SDCLKL _Data)

Data output hold time

0.5

td(SDCLK _Add)

Address valid time

td(SDCLKL _SDNWE)) SDNWE valid time

th(SDCLKL_SDNWE)) SDNWE hold time

td(SDCLKL_SDNE))

Chip select valid time

2.5

th(SDCLKL_ SDNE)

Chip select hold time

td(SDCLKL_SDNRAS) SDNRAS valid time

th(SDCLKL_SDNRAS) SDNRAS hold time

td(SDCLKL_SDNCAS) SDNCAS valid time

td(SDCLKL_SDNCAS) SDNCAS hold time

Table 104. DCMI characteristics

Symbol

Parameter

Min

Max

Unit

Frequency ratio DCMI_PIXCLK/fHCLK

-0.4

DCMI_PIXCLK Pixel clock input

MHz

DPixel

Pixel clock input duty cycle

tsu(DATA)

Data input setup time

th(DATA)

Data input hold time

3.5

tsu(HSYNC)

tsu(VSYNC)

DCMI_HSYNC/DCMI_VSYNC input setup time

th(HSYNC)

th(VSYNC)

DCMI_HSYNC/DCMI_VSYNC input hold time

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