STM32F446RC datasheet(78/201 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F446xC/E

78/201

DocID027107 Rev 5

6.3.2

VCAP_1/VCAP_2 external capacitor

Stabilization for the main regulator is achieved by connecting external capacitor CEXT to the

VCAP_1 and VCAP_2 pin. For packages supporting only 1 VCAP pin, the 2 CEXT capacitors are

replaced by a single capacitor. CEXT is specified in Table 18.

1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.

2. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.16.2:

Internal reset OFF).

3. When the ADC is used, refer to Table 74: ADC characteristics.

4. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.

5. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and

VDDA can be tolerated during power-up and power-down operation.

6. The over-drive mode is not supported when the internal regulator is OFF.

7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled

8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.

9. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.

Table 17. Limitations depending on the operating power supply range

Operating

power supply

range

ADC operation

Maximum Flash

memory access

frequency with

no wait states

(fFlashmax)

Maximum HCLK

frequency vs Flash

memory wait states

(1)(2)

I/O operation

Possible Flash

memory

operations

VDD =1.7 to

2.1 V(3)

Conversion time

up to 1.2 Msps

20 MHz(4)

168 MHz with 8 wait

states and over-drive

OFF

– No I/O

compensation

8-bit erase and

program

operations only

VDD = 2.1 to

2.4 V

Conversion time

up to 1.2 Msps

22 MHz

180 MHz with 8 wait

states and over-drive

– No I/O

compensation

16-bit erase and

program

operations

VDD = 2.4 to

2.7 V

Conversion time

up to 2.4 Msps

24 MHz

180 MHz with 7 wait

states and over-drive

– I/O

compensation

works

16-bit erase and

program

operations

VDD = 2.7 to

3.6 V(5)

Conversion time

up to 2.4 Msps

30 MHz

180 MHz with 5 wait

states and over-drive

– I/O

compensation

works

32-bit erase and

program

operations

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is

required.

2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the

execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state

program execution.

3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.16.2:

Internal reset OFF).

4. Prefetch is not available.

5. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+

pins will be degraded between 2.7 and 3 V.

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