SPEAR320S datasheet(47/113 Pages) STMICROELECTRONICS

47 / 113 page

Note:

Table 15 cells filled with ‘0’ or ‘1’ are unused and unless otherwise configured as Alternate function or GPIO, the corresponding pin

is held at low or high level respectively by the internal logic.

2Pins shared by EMI and FSMC: Depending on the AHB address to be accessed the pins are used for EMI or FSMC transfers.

3Reset state definition: the state of each pin during reset and after reset release. Device is in configuration mode 1 (default state) :

OH= Output high level, OL output low level, IPU = input pull up, IPD = input pull down.

Full debug mode: refer to Table 32: Ball sharing during debug for details on debug mode selection.

Functional mode definition: in functional mode the I/O works as configured by the application (depending on settings for

Configuration mode 1- 4/Extended mode/Alternate function).

Refer to Table 16: Table shading reference for Table 15 multiplexing scheme for colors and shading used in Table 15 cells to

identify pin groups

PL_GPIO_5/D2

UART1_RI

I2C0_SDA

Functional mode

IPU

GPIO_5

UART5_TX

PL_GPIO_4/C1

UART1_DCD

I2C0_SCL

IPU

GPIO_4

UART5_RX

PL_GPIO_3/D1

UART1_DSR

UART0_RX

IPD

GPIO_3

I2C2_SDA

UART6_TX

PL_GPIO_2/E4

UART1_RTS

UART0_TX

GPIO_2

I2C2_SCL

UART6_RX

PL_GPIO_1/E3

I2C2_SDA

IrDA_RX

IPU

GPIO_1

UART2_TX

PL_GPIO_0/F3

I2C2_SCL

IrDA_TX

GPIO_0

UART2_RX

PL_CLK1/K17

UART3_TX

PL_CLK1

GPIO_98

CLCP

I2C1_SDA

SD_LED

PL_CLK2/J17

UART3_RX

PL_CLK2

GPIO_99

SD_CLK

I2C1_SCL

SD_CLK

PL_CLK3/J16

UART4_TX

PL_CLK3

IPU

GPIO_100

SD_WP

PL_CLK4/H17

UART4_RX

PL_CLK4

IPU

GPIO_101

SD_CMD

Table 15.

PL_GPIO/PL_CLK multiplexing scheme and reset states (continued)

PL_GPIO_# /

ball number

Extended

mode

primary

function (SW

defined)

Alternate

function

(SW

defined)

Full debug mode

Legacy configuration mode (SW defined)

Mode 1

(Default

configuration

after reset)

Mode 2

Mode 3

Mode 4

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