SPEAR320S datasheet(24/113 Pages) STMICROELECTRONICS

24 / 113 page

Device functions

SPEAr320S

24/113

Doc ID 022508 Rev 2

2.22

JPEG codec accelerator (JPGC)

SPEAr320S provides an integrated hardware accelerator for decoding and encoding

standard JPEG images.

JPEG data streams to be decoded must be compliant with the interchange format syntax

specified in the ISO/IEC 10918-1. The JFIF image file format is also supported through

header processing.

The output format for decoding (and input format for encoding) is a MCU stream, not a

conventional bitmap format like RGB. Displaying a decoded JPEG still picture would require

further steps and algorithms like color space conversion and scaling.

Main features:

●

Compliance with the baseline JPEG standard (ISO/IEC 10918-1)

●

Single-clock per pixel encoding/decoding

●

Support for up to four channels of component color

●

8-bit/channel pixel depths

●

Programmable quantization tables (up to four)

●

Programmable Huffman tables (two AC and two DC)

●

Programmable minimum coded unit (MCU)

●

Configurable JPEG header processing

●

Support for restart marker insertion

●

Use of two DMA channels and two 8 x 32-bit FIFOs (local to the JPEG) for efficient

transferring and buffering of encoded/decoded data from/to the Codec core.

2.23

Digital audio port (I2S)

The SPEAr320S integrates a digital audio port compliant to standard I2S (Philips)

specifications.

Main features:

●

I2S master mode

●

Stereo (2.0) playback and recording

●

Support for standard sampling rates (8, 16, 32, 44.1, 48, 96, 192 kHz); the clock input is

24 MHz, so the rate precision depends on the chosen rate and divider.

●

Support of a range of audio samples: 12 / 16 / 20 / 24/ 32 bits

●

Programmable thresholds for internal FIFO queues

●

Capability of using DMA transfer

2.24

Cryptographic co-processor (C3)

SPEAr320S provides an embedded cryptographic co-processor (C3). C3 is a high-

performance instruction-driven DMA-based engine that can be used to accelerate the

processing of security algorithms.

After its initial configuration by the main CPU, it runs in a completely autonomous way (DMA

data in, data processing, DMA data out), until the completion of all the requested operations.

C3 firmware is fetched from system memory.

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