SPEAR320S datasheet(12/113 Pages) STMICROELECTRONICS

12 / 113 page

Device functions

SPEAr320S

12/113

Doc ID 022508 Rev 2

The BootROM firmware selects the boot mode from the boot pin settings (see Section 3.4.5:

Boot pins). A setting is also available to allow the BootROM execution to be bypassed.

The first three modes support alternate ways of locating and starting the selected operating

system or target custom software. Such modes require a second-level boot firmware to be

stored in external Flash memory. A reference code for such boot loader (called “XLoader”) is

provided by STMicroelectronics in source and binary formats for the SPEAr320S evaluation

boards. Such code must be adapted according to the specific DDR memory components

found on target customer systems.

The fourth mode can be used for installing and updating the software on external Flash

memories through a PC-based software utility provided by STMicroelectronics exploiting a

USB link between a PC and a target SPEAr320S board.

The sixth mode used the MII0 port and is based on two standard protocols: DHCP (to get an

IP address over the network) and TFTP (for receiving xloader and u-boot binary images).

2.3

Multiport DDR controller (MPMC)

SPEAr320S integrates a high-performance controller able to manage DDR2 (double data

rate) and LPDDR (low power DDR) external dynamic memory devices.

Main features:

●

Support for DDR2 up to 333 MHz (666 MT/sec)

●

Support for LPDDR up to 166 MHz (333 MT/sec)

●

Support for 8-/16-bit external data bus

●

Support for up to 1 GByte DDR2/LPDDR memory address space

●

Full initialization of memories on controller reset

●

6 independent internal ports: five of them are used to access the external memory

while one is reserved for programming the controller configuration registers

●

Programmable built-in port arbitration scheme to ensure high memory bandwidth

utilization

●

Fully pipelined read and write commands

●

Self-refresh mode for power saving

●

Integrated physical layer (PHY) and delay locked loops (DLLs) for fine tuning of the

timing parameters, maximizing the data valid windows at different frequencies

2.4

Serial NOR Flash controller (SMI)

SPEAr320S integrates a Flash memory controller able to manage serial, SPI-compatible,

NOR Flash and EEPROM external memory devices.

Main features:

●

Support for up to 32 MByte external serial memory storage capacity (2 x 16 MB

addressable banks by independent chip select signals)

●

SMI clock up to 50 MHz (fast read mode) or 20 MHz (normal mode), with software

configurable 7-bit prescaler

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