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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPEAR320S датащи(PDF) 70 Page - STMicroelectronics |
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SPEAR320S датащи(HTML) 70 Page - STMicroelectronics |
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70 / 113 page  Electrical characteristics SPEAr320S 70/113 Doc ID 022508 Rev 2 4.6 Clocking parameters 4.6.1 Master clock (MCLK) MCLK generated from a crystal oscillator Figure 4. MCLK crystal connection 1. CL1 and CL2 are the load capacitors. The value of the capacitors depends on the type of the selected crystal. To calculate the value of the load capacitance, use the formula given below. Formula C L C L1 C L2 × C L1 C L2 + -------------------------- C s + = Where CL1 and CL2 are the load capacitors and CS is the circuit stray capacitance. In our application: CL1 = CL2 = Cext Table 40. MCLK oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fosc_in Oscillator frequency 24(1) 1. A frequency of 24 MHz is mandatory to obtain the required frequencies for all clocks generated by the USB PLL (PLL3). 33 (2) 2. At Max freq = 33 MHz the ESR value has to be less than 20 Ω. MHz ESR Equivalent series resisistance 50 Ω gm Oscillator transconductance Startup 19.8 28.5 mA/V tSU Startup time Stabilized power on MCLK_VDD2V5 pin 2 (3) 3. Startup time simulated with a 30 MHz crystal. ms VDD2V5 24 MHz CL1 CL2 (1) (1) MCLK_XI MCLK_XO |
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