MEC1322 datasheet(136/456 Pages) MICROCHIP

136 / 456 page

MEC1322

DS00001719D-page 136

 2014 - 2015 Microchip Technology Inc.

10.12.5

ACPI OS COMMAND REGISTER

10.12.6

OS STATUS OS REGISTER

This read-only register is aliased to the EC STATUS Register on page 143. the EC STATUS Register on page 143 has

read write access.

Offset

04h

Bits

Description

Type

Default

Reset

Event

7:0 ACPI_OSS_COMMAND

Writes to the this register are aliased in the OS2EC Data EC Byte 0

Writes to the this register also set the CMD and IBF bits in the OS

STATUS OS Register

W0h

VCC1_R

ESET

Offset

04h

Bits

Description

Type

Default

Reset

Event

7UD0B

User Defined

R0b

VCC1_R

ESET

6 SMI_EVT

This bit is set when an SMI event is pending; i.e., the ACPI_EC is

requesting an SMI query; This bit is cleared when no SMI events

are pending.

This bit is an ACPI_EC-maintained software flag that is set when

the ACPI_EC has detected an internal event that requires system

management interrupt handler attention. The ACPI_EC sets this bit

before generating an SMI.

Note:

The usage model from the ACPI specification requires

both SMI’s and SCI’s. The ACPI_OS SMI & SCI inter-

rupts are not implemented in the ACPI Embedded Con-

troller Interface (ACPI-ECI). The SMI_EVT and

SCI_EVT bits in the OS STATUS OS Register are soft-

ware flags and this block do not initiate SMI or SCI

events.

R0b

VCC1_R

ESET

5 SCI_EVT

This bit is set by software when an SCI event is pending; i.e., the

ACPI_EC is requesting an SCI query; SCI Event flag is clear when

no SCI events are pending.

This bit is an ACPI_EC-maintained software flag that is set when

the embedded controller has detected an internal event that

requires operating system attention. The ACPI_EC sets this bit

before generating an SCI to the OS.

Note:

The usage model from the ACPI specification requires

both SMI’s and SCI’s. The ACPI_OS SMI & SCI inter-

rupts are not implemented in the ACPI Embedded Con-

troller Interface (ACPI-ECI). The SMI_EVT and

SCI_EVT bits in the OS STATUS OS Register are soft-

ware flags and this block do not initiate SMI or SCI

events.

R0b

VCC1_R

ESET

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